Openocd configuration file for i.mx8qxp

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Openocd configuration file for i.mx8qxp

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jing_xu1
Contributor II

I want to use Openocd+JLink to debug IMX8QualMaxPlus MEK Board,  but there is no target/imx8qxp.cfg or board/nxp_mcimx8qxp-mek.cfg in /path/to/openocd/tcl/,so i made target/imx8qxp.cfg by myself refer to target/imx8m.cfg, however, i found that i can't send commands such as 'halt','reset' to the , maybe coresight base addresses of imx8m aren't apply to the i.mx8qxq?

My own imx8qxp.cfg:

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME imx8
}
if { [info exists CHIPCORES] } {
    set _cores $CHIPCORES
} else {
    set _cores 1
}
# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x1890201d
}
# the DAP tap
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.a53
set _CTINAME $_CHIPNAME.cti
set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
for { set _core 0 } { $_core < $_cores } { incr _core } {
    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
        -ctibase [lindex $CTIBASE $_core]
    set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command $_TARGETNAME.$_core"
    } else {
        set _smp_command "target smp $_TARGETNAME.$_core"
    }
    eval $_command
}
eval $_smp_command
# declare the auxiliary Cortex-M4 core on AP #4
# target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
               -defer-examine
# AHB-AP for direct access to soc bus
target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
# default target is A53 core 0
targets $_TARGETNAME.0

After i input 'dap info 1', these are output info:

> dap info 1
AP ID register 0x24770011
 Type is MEM-AP AHB3
MEM-AP BASE 0xe00ff003
 Valid ROM table present
  Component base address 0xe00ff000
  Peripheral ID 0x04000bb4c4
  Designer is 0x4bb, ARM Ltd.
  Part is 0x4c4, Cortex-M4 ROM (ROM Table)
  Component class is 0x1, ROM table
  MEMTYPE system memory present on bus
 ROMTABLE[0x0] = 0xfff0f003
  Component base address 0xe000e000
  Peripheral ID 0x04000bb00c
  Designer is 0x4bb, ARM Ltd.
  Part is 0xc, Cortex-M4 SCS (System Control Space)
  Component class is 0xe, Generic IP component
 ROMTABLE[0x4] = 0xfff02003
  Component base address 0xe0001000
  Invalid CID 0x00000000
 ROMTABLE[0x8] = 0xfff03003
  Component base address 0xe0002000
  Peripheral ID 0x04002bb003
  Designer is 0x4bb, ARM Ltd.
  Part is 0x3, Cortex-M3 FPB (Flash Patch and Breakpoint)
  Component class is 0xe, Generic IP component
 ROMTABLE[0xc] = 0xfff01003
  Component base address 0xe0000000
  Invalid CID 0xb1b1b1b1
 ROMTABLE[0x10] = 0xfff41002
  Component not present
 ROMTABLE[0x14] = 0xfff42003
  Component base address 0xe0041000
  Peripheral ID 0x04000bb925
  Designer is 0x4bb, ARM Ltd.
  Part is 0x925, Cortex-M4 ETM (Embedded Trace)
  Component class is 0x9, CoreSight component
  Type is 0x13, Trace Source, Processor
 ROMTABLE[0x18] = 0xfff43002
  Component not present
 ROMTABLE[0x1c] = 0xfff44003
  Component base address 0xe0043000
  Peripheral ID 0x04001bb908
  Designer is 0x4bb, ARM Ltd.
  Part is 0x908, CoreSight CSTF (Trace Funnel)
  Component class is 0x9, CoreSight component
  Type is 0x12, Trace Link, Funnel, router
 ROMTABLE[0x20] = 0x0
  End of ROM table

Could you please provide the whole imx8qxp.cfg?

Thanks,

Jing

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645 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Jing

for openocd one can look on below links

https://community.nxp.com/thread/480454 

https://community.nxp.com/thread/434323?commentID=830709#comment 

what is imx8 core base for jtag ~~Help 

Best regards
igor
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