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what is imx8 core base for jtag ~~Help

Question asked by jesse stone on Feb 6, 2018
Latest reply on Mar 16, 2018 by jesse stone

for jtag openocd

 

I get BSDL file for i.MX 8M (REV 1)  

it's 0x1cf80553 for sjc_tapid

# System JTAG Controller
if { [info exists SJC_TAPID] } {
        set _SJC_TAPID $SJC_TAPID
} else {
        set _SJC_TAPID 0x1cf80553
}
set _SJC_TAPID2 0x2cf80553

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2

 

now i.mx8

1. need Base addresses of cores

2. CoreSight Debug Access Port

 

///////////////////////////////////////////////////////////////////////

this is for arm arch64

///////////////////////////////////////////////////////////////////////

set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {

    set _command "target create ${_TARGETNAME}$_core aarch64 \
                         -chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"

    if { $_core != 0 } {
        # non-boot core examination may fail
        set _command "$_command -defer-examine"
        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
    } else {
        # uncomment when "hawt" rtos is merged
        # set _command "$_command -rtos hawt"
        set _smp_command "target smp ${_TARGETNAME}$_core"
    }

    eval $_command
}

eval $_smp_command

# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine

 

 

///////////////////follow is for imx.6 info ///////////////////

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
        set _DAP_TAPID $DAP_TAPID
} else {
        set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller
if { [info exists SJC_TAPID] } {
        set _SJC_TAPID $SJC_TAPID
} else {
        set _SJC_TAPID 0x0191c01d
}
set _SJC_TAPID2 0x0191e01d
set _SJC_TAPID3 0x2191c01d
set _SJC_TAPID4 0x2191e01d

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
        -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4

# GDB target: Cortex-A9, using DAP, configuring only one core
# Base addresses of cores:
# core 0  -  0x82150000
# core 1  -  0x82152000
# core 2  -  0x82154000
# core 3  -  0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
        -coreid 0 -dbgbase 0x82150000

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