Something is puzzling me and would be glad if someone could clear it up. On iMX side NANDF_WP_B pin is described as wait polarity signal. On the NAND flash I have selected, the pin NANDF_WP_B is the hardware write protection pin.
On Sabre AI platform, these two signals are connected so can someone confirm wait polarity and write protection serve the same functionality?
Regards,
Mete
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Hi Mete
it is write protection pin. Description as " wait polarity signal"
was left as gpmi can also work with ata devices (not supported in this chip).
Best regards
igor
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Hi Mete
it is write protection pin. Description as " wait polarity signal"
was left as gpmi can also work with ata devices (not supported in this chip).
Best regards
igor
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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Hi Igor,
Thank you for the information.
Best Regards,
Mete