MIPI DSI Driver strength

[kunal_003]

Hi,

We are using i.MX8M Plus for our design. Can we modify the drive strength of Clock and Data in MIPI DSI HS mode? If yes, Is it with some property in device tree or we need to modify registers in driver?

Thank you in advance !

Regards,

Kunal

[Mihir2]

Hello NXP team,

We have verified MIPI DSI clock signal on iMX8MPlus EVK and our design (based on iMX8MPlus) , while playing 1080p videos on both interface.

Below are our observations:

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1. As per MIPI DSI D-PHY specifications v1.2 --> Table 19, maximum differential voltage (high side or low side ) is 270 mV. This corresponds to maximum peak to peak voltage of 540 mV.
2. While playing 1080p video on EVK, MIPI DSI clock has been measured at 473 mV peak to peak (within specifications) and DSI interface is working fine!!
3. While playing 1080p video on our custom design board, MIPI DSI cloak has been measured at 900 mV peak to peak (outside specifications), still DSI interface on our board is working fine. 

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Please suggest if we have to change any configuration / drive strength on our custom board so that we do not violate MIPI specifications. 

Thanks.

[Mihir2]

Hello NXP team,

We have reviewed our board layout with reference to i.MX 8M+ hardware developer's guide as well as NXP EVK design.

We did not find any issue (All the traces are routed differentially, solid GND plane as a reference and length-matched. Also, we verified impedance report from PCB FAB house, and all single ended / differential impedances are within 10% tolerance.)

Kindly guide us for further investigation / troubleshooting.

Thanks.

[Mihir2]

Hello NXP team,

Please guide for further investigation and troubleshooting.

Thanks.

[Mihir2]

Hello NXP team,

Please provide any suggestions for troubleshooting so that we can fix this issue before our 2nd board re-spin.

Thanks.

[igorpadykov]

in general,  support for passing compliance specifications is provided with NXP Professional Services:
https://contact.nxp.com/new-prof-svcs-sw-tech

Best regards
igor

[igorpadykov]

Hi Mihir

>if we have to change any configuration / drive strength on our custom board so

>that we do not violate MIPI specifications. 

this is caused by board layout (impedance mismatch) and can not be changed by software settings.

Recommended to review board layout using  i.MX 8M Plus Hardware Developer’s Guide

and NXP EVK design

https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-...

Best regards
igor

[Mihir2]

Hi NXP team,

This is Mihir, working with Kunal on the same design.

We are checking MIPI DSI signal levels for Design Validation Testing.

We found that, MIPI DSI Clock and Data signal levels are not compliant with MIPI D-PHY specifications v1.2. Hence, we would like to see if any register settings can be changed to reduce overall signals peak to peak value?

Thanks,

[igorpadykov]

please test it on NXP i.MX8M Plus EVK reference board

https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-...

Best regards
igor

[igorpadykov]

Hi Kunal

mipi-dsi drive strength and output levels are defined and guaranteed by specifications

and cannot be programmed.

Best regards
igor