Hello to NXP Community,
i am trying to Bring-up Digiwise's 13-070WMLBIAG1- C 7" display with TechNexion EDM-G-IMX8MM and WB baseboard custom board.
The changes i did in .dts and panel-simple.c as per datasheet mentioned here. The source code is Android - 11 by https://github.com/technexion-android/.
DTS file : ... / dts/freescale/overlays/imx8mm-edm-g-wb-sn65dsi84-vl10112880-overlay.dts
fragment@1 {
target = <&mipi_dsi>;
__overlay__ {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
reg = <0>;
compatible = "tn,dsi2lvds-panel";
backlight = <&lvds_backlight>;
power-supply = <®_lvds_pwr>;
dsi,flags = <0x0007>;
dsi,format = <2>;
dsi,lanes = <4>;
panel-width-mm = <152>;
panel-height-mm = <91>;
bus-format = <0x1009>; /* MEDIA_BUS_FMT_RGB666_1X18 */
bus-flags = <1>;
refresh-rate = <60>;
rotate = <0>;
/* horz-flip; */
/* vert-flip; */
panel-timing {
clock-frequency = <33300000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <204>;
hsync-len = <6>;
hback-porch = <46>;
vfront-porch = <22>;
vsync-len = <3>;
vback-porch = <23>;
/* flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH */
vsync-active = <1>;
hsync-active = <1>;
};
};
};
};
And in .... / drivers/gpu/drm/panel/panel-simple.c
static const struct display_timing dsi2lvds_panel_timing = {
.pixelclock = { 26400000, 33300000, 46800000},
.hactive = { 800, 800, 800},
.hfront_porch = { 16, 204, 354 },
.hback_porch = { 46, 46, 46 },
.hsync_len = { 1, 6, 40 },
.vactive = { 480, 480, 480 },
.vfront_porch = { 7, 22, 147 },
.vback_porch = { 23, 23, 23 },
.vsync_len = { 1, 3, 20 },
.flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH,
};
/*
* @modes: Pointer to array of fixed modes appropriate for this panel. If
* only one mode then this can just be the address of this the mode.
* NOTE: cannot be used with "timings" and also if this is specified
* then you cannot override the mode in the device tree.
* @num_modes: Number of elements in modes array.
* @timings: Pointer to array of display timings. NOTE: cannot be used with
* "modes" and also these will be used to validate a device tree
* override if one is present.
* @num_timings: Number of elements in timings array.
* @bpc: Bits per color.
* @size: Structure containing the physical size of this panel.
* @delay: Structure containing various delay values for this panel.
* @bus_format: See MEDIA_BUS_FMT_... defines.
* @bus_flags: See DRM_BUS_FLAG_... defines.
* @refresh_rate: Refresh rate, e.g. 60MHz
* @rotate: Rotation, e.g. 0, 90, 180, 270 degrees
* @hflip: Horizontal flip, e.g. flip horizontally
* @vflip: Vertical flip, e.g. flip vertically
*/
static const struct panel_desc_dsi dsi2lvds_panel = {
.desc = {
.timings = &dsi2lvds_panel_timing,
.num_timings = 1,
.bpc = 6,
.size = {
.width = 152,
.height = 91,},
.bus_flags = DRM_BUS_FLAG_DE_LOW,
},
.flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
.format = MIPI_DSI_FMT_RGB666,
.lanes = 4,
};
in result adb shell >> dmesg
edm_g_imx8mm:/ # dmesg | grep -i dsi
[ 0.625461] imx_sec_dsim_drv 32e10000.mipi_dsi: failed to get blk_ctl
[ 0.625627] imx_sec_dsim_drv 32e10000.mipi_dsi: version number is 0x1060200
[ 0.625913] imx_sec_dsim_drv 32e10000.mipi_dsi: Failed to attach bridge: 32e10000.mipi_dsi
[ 0.634275] imx_sec_dsim_drv 32e10000.mipi_dsi: failed to bind sec dsim bridge: -517
[ 0.916209] sn65dsi84 0-002d: Valid sn65dsi84 chip id
[ 0.952430] sn65dsi84 0-002d: Soft reset to default
[ 1.080725] imx_sec_dsim_drv 32e10000.mipi_dsi: failed to get blk_ctl
[ 1.080853] imx_sec_dsim_drv 32e10000.mipi_dsi: version number is 0x1060200
[ 1.081031] panel-simple-dsi 32e10000.mipi_dsi.0: >>>>Initial DSI config: flags = 1025, format = 1, lanes = 4
[ 1.081040] panel-simple-dsi 32e10000.mipi_dsi.0: >>>>Final DSI config: flags = 7, format = 2, lanes = 4
[ 1.081045] panel-simple-dsi 32e10000.mipi_dsi.0: panel-desc-dsi setting overridden from dt
[ 1.081057] panel-simple-dsi 32e10000.mipi_dsi.0: panel-desc setting overridden from dt
[ 1.081187] panel-simple-dsi 32e10000.mipi_dsi.0: Found suitable override.
[ 1.081251] imx-drm soc@0:bus@32c00000:display-subsystem: bound 32e10000.mipi_dsi (ops imx_sec_dsim_ops)
[ 1.084469] imx_sec_dsim_drv 32e10000.mipi_dsi: >>>DSI format: 4105, DSI clock = 33300
[ 1.084479] imx_sec_dsim_drv 32e10000.mipi_dsi: Chirag ==> imx_sec_dsim_encoder_helper_atomic_check:144 display_info->bus_formats[i]: 4105 bus_format:4105 num_bus_formats: 1
[ 1.106707] imx_sec_dsim_drv 32e10000.mipi_dsi: >>>DSI format: 4105, DSI clock = 33300
[ 1.106713] imx_sec_dsim_drv 32e10000.mipi_dsi: Chirag ==> imx_sec_dsim_encoder_helper_atomic_check:144 display_info->bus_formats[i]: 4105 bus_format:4105 num_bus_formats: 1
[ 14.191421] imx_sec_dsim_drv 32e10000.mipi_dsi: >>>DSI format: 4105, DSI clock = 33300
[ 14.191432] imx_sec_dsim_drv 32e10000.mipi_dsi: Chirag ==> imx_sec_dsim_encoder_helper_atomic_check:144 display_info->bus_formats[i]: 4105 bus_format:4105 num_bus_formats: 1
[ 15.078433] imx_sec_dsim_drv 32e10000.mipi_dsi: >>>DSI format: 4105, DSI clock = 33300
[ 15.078442] imx_sec_dsim_drv 32e10000.mipi_dsi: Chirag ==> imx_sec_dsim_encoder_helper_atomic_check:144 display_info->bus_formats[i]: 4105 bus_format:4105 num_bus_formats: 1
[ 15.528918] imx_sec_dsim_drv 32e10000.mipi_dsi: >>>DSI format: 4105, DSI clock = 33300
[ 15.528927] imx_sec_dsim_drv 32e10000.mipi_dsi: Chirag ==> imx_sec_dsim_encoder_helper_atomic_check:144 display_info->bus_formats[i]: 4105 bus_format:4105 num_bus_formats: 1
and here is screenshot : 
* >>> However below mentioned changes in panel-simple.c :
static const struct panel_desc_dsi dsi2lvds_panel = {
.desc = {
.timings = &dsi2lvds_panel_timing,
.num_timings = 1,
.bpc = 8,
.size = {
.width = 165,
.height = 105,
.width = 152,
.height = 91,
},
.bus_flags = DRM_BUS_FLAG_DE_LOW,
},
static const struct panel_desc_dsi dsi2lvds_panel = {
.format = MIPI_DSI_FMT_RGB888,
.lanes = 4,
};
i got this result : 
Despite this, I am facing issues with display initialization, and the panel does not seem to power up as expected. Could someone please assist me in reviewing the device tree configuration or suggest any required changes in the driver code (panel-simple.c) or other areas to help resolve this issue?
Additionally, any insights on changes that may be required in the SN65DSI84 bridge configuration or the DRM driver (panel-simple.c) would be appreciated.
Thank you for your support!
Best regards,
Ajaysinh.
