LVDS display configuration on MCIMX6Q5EYM10AD

[Jack-Cha]

Hi Champs

There's a question from Customer who wants to port LVDS panel on MCIMX6Q5EYM10AD.

The following is the panel timing specification. 

The below dtsi is below to support their panel.

lvds-channel@0 {

fsl,data-mapping = "spwg";

fsl,data-width = <18>;

primary;

status = "okay";

display-timings {

native-mode = <&timing0>;

timing0: 800x480@60 {

clock-frequency = <25000000>;

hactive = <800>;

vactive = <480>;

hback-porch = <8>;

hfront-porch = <8>;

vback-porch = <8>;

vfront-porch = <8>;

hsync-len = <4>;

vsync-len = <4>;

};

};

};

According to their test observed, the video output clock runs 38MHz (pclk TCLK+, TCLK-) even though the clock set to 25MHz.

If clock speed sets up to 39MHz over, it runs normally. It always runs 38MHz when sets up under 39MHz. 

Please clarify the followings

1. iMX6' LVDS Minimum Resolution.

2. Guidance to support 800x480 (25MHz), or patch(code changes needed)

Thanks.

Regards, 

James

[joanxie]

if you need to set lower resolution, you need change the clock parent, pls see this document：

“https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Porting-LVDS-LCD-With-Low-Resolution-to-...