LPDDR4 RPA configuration with custom iMX8M Plus Board

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LPDDR4 RPA configuration with custom iMX8M Plus Board

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maxime_guillot
Contributor III

Hello,

When trying to run the DDR training, the following error occurs, while using Mscale_ddr_tool _v3.20:

"PMU: Error: CA Training Failed.
PMU: ***** Assertion Error - terminating *****"

Find attached the MX8M_Plus_LPDDR4_RPA_v6 for my 4GB LPDDR4.

Further infos:

- Custom board using i.MX8M-Plus

- LDDR4+eMMC: FORESEE_eMCP_FEPRF6432-58A1930 Twin die (please see datasheet attached p34)

Could you please check my RPA (xlsx) configuration attached?

The datasheet says "number of ROW adress R[16:0] but it seems invalid for the RPA files.

Thank you

 

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Maxime

 

from team:

-------------------------

I'm not very clear about customer's DDR configuration.

From the DDR device datasheet they used is a two die ddr, and one channel in one die, and 16Gb per die, and 16dq per die.

So, if customer want to config 32bit, they just need config two channels and one "chip select".

What does customer mean "use 2 chip select per channel". 8Gb per channel per chip select is not allowed in datasheet.

-------------------------

 

Best regards
igor

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Danube
Contributor IV

Hi Maxime,

 

I also had this issue before.

But I had change USB1_VBUS input.

R71 = 30K , R72 is DNP.

It can finish DDR calibration function.

Just share this information to you.

My DRAM is single die 16Gbit. , DRAM total size is 32Gbit.

 

Danube_0-1622948427467.png

 

Danube_1-1622948554994.png

 

 

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maxime_guillot
Contributor III

Another update.

When I configure the DDR as 32 bit with only 1 chip select used, the training works. But when I want to use 2 chip select per channel, the trainning fails. Can you help on this topic?

See RPA 32 bits attached.

 

Thank you

 

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igorpadykov
NXP TechSupport
NXP TechSupport

could you please provide part of schematic with ddr connections.

 

Best regards
igor

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maxime_guillot
Contributor III

Find attached the LPDDR4 Sch.

Thanks

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1,400 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Maxime

 

from team:

-------------------------

I'm not very clear about customer's DDR configuration.

From the DDR device datasheet they used is a two die ddr, and one channel in one die, and 16Gb per die, and 16dq per die.

So, if customer want to config 32bit, they just need config two channels and one "chip select".

What does customer mean "use 2 chip select per channel". 8Gb per channel per chip select is not allowed in datasheet.

-------------------------

 

Best regards
igor

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maxime_guillot
Contributor III

Hello,

As I said, I use 4GB LPDDR4 with 1 CS per channel of 16Gb as shown in the RPA file attached. So for me it seems ok, I have 2 channels with 1 CS on each channel then 32Gb memory.

maxime_guillot_0-1623494352165.png

But when I start the DDR stress test, it shows that I have 1 CS with 32GB :

maxime_guillot_1-1623494420166.png

I would expect 2 CS with 4GB or 1CS with 2GB. The total is ok but I am having problem with the memory map in early Android boot with this config. Can you confirm my config is ok?

Thank you

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maxime_guillot
Contributor III

An update on my DDR test.

When I configure the DDR as a single 16bit bus, it works fine. The training is sucessful.

See RPA 16 DDR config attached

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