L2 cache for MCIMX6G0DVM05AA ?

[CarstenBode]

Hello together,

I´m not sure if the smallest IMX6UL has a L2 cache:

The block diagram that shows the optional block dottet indicates the presence of 128k L2C on all versions.

The datasheet only refers to the feature set Baseline/ General purpose 1 and 2 and security, no details.

The UL Fact sheet shows no L2 cache for the G0 version.

[gusarambula · Accepted solution]

Hello Carsten Bode,

As you mentioned, the L2 cache block is marked as optional in some i.MX6UL Part Numbers. The G0 version of the i.MX6UL is the less equipped of the i.MX6UL processors and indeed does not have L2 Cache so the information on the Fact Sheet is correct. If this is a requirement for your design I would recommend using the G1 version.

I hope this information helps!

[CarstenBode]

Hello gusarambulo,

ok, thanks for the clarification, I understand that the L2 cache block is missing.

I assume the SCU is still present because it is separate from the L2C on the Corte A7.

Best regards

Carsten

[gusarambula]

Hello Carsten Bide,

You are correct, the SCU is still present even if no L2 cache is available.

Regards,