L2 cache enabled

[MarkoPanger]

Hi all,

Searching through the kernel sources I haven't found a point where L2 cache is enabled. Off course I might be wrong, but it seems L2 isn't enabled anywhere.

I'm using the i.mx50 distribution the L2.6.35_11.04.01 LTIB distribution.

Does somebody with more knowledge than me confirm this ?

Thanks, Marko

[MarkoPanger]

Thanks Fabio for pointing this out. Pretty confusing design by enabling portions of HW here and there.

My interest for L2 started when I've noticed that NEON pld instruction wasn't having any effect. So I wanted to check if the bits for enabling this instruction are set in cp15.

Marko

Fabio Estevam said:

L2 cache is enabled in the bootloader.

See cpu/arm_cortexa8/mx50/generic.c:

http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=cp...

[fabio_estevam]

L2 cache is enabled in the bootloader.

See cpu/arm_cortexa8/mx50/generic.c:

http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=cpu/arm_cortexa8/mx50/generic.c;h=e...