Trouble bringing up USB1 in U-Boot (i.mx287)

[SimonBudig]

Hi all. I have problems bringing up USB1 in U-Boot. I am a little bit stuck in starting up the PHY. The Datasheet claims on page 1963 that I'd have to clear "HW_POWER_CTRL_CLKGATE" - I searched the documentation up and down and I just don't find this CLKGATE. Can somebody point me to some USB1 initialization code? Or resolve this discrepancy in the datasheet? Thanks, Simon

[admin]

Hi,

         Please let me know, whether you are using the iMX28EVK board or custom board. if you are using the imx28EVK board then follow below process to make it work.

1. Need to enable the setting for USB OC (PINID_SSP2_SS1) pin along with enabling the USB1 EN (PINID_AUART2_RX) pin.

2. Check the below lines for init USB1

usbphy = (struct mx28_usbphy *)REGS_USBPHY1_BASE;

    /* Reset the PHY block */
    writel(USBPHY_CTRL_SFTRST, &usbphy->usbphy_ctrl + SET);
    udelay(10);
    writel(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE,
        (&usbphy->usbphy_ctrl + CLR));

    /* Enable USB clock */
    writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
            (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLL1CTRL0 + CLK_SET));
    writel(CLKCTRL_PLL1CTRL0_EN_USB_CLKS | CLKCTRL_PLL1CTRL0_POWER,
            (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLL1CTRL0 + CLK_SET));
   
    /* Gate on the USB clock */
    writel(HW_DIGCTL_CTRL_USB0_CLKGATE | HW_DIGCTL_CTRL_USB1_CLKGATE,
        (REGS_DIGCTL_BASE + CLK_CLR));

    /* Start USB PHY */
    writel(0, &usbphy->usbphy_pwd);

    /* Enable UTMI+ Level 2 and Level 3 compatibility */
    writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1,
        (&usbphy->usbphy_ctrl + SET));

    usb_base = ((uint32_t)(REGS_USBCTRL1_BASE + 0x100));
    hccr = (struct ehci_hccr *)usb_base;

    cap_base = ehci_readl(&hccr->cr_capbase);
    hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));