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Hello,
I am optimizing the power consumption of an embedded device based on the iMX6UL processor. My aim is to leave it sleeping as long as possible, using the EPIT to wake it up regularly as needed.
Currently, I am able (thanks to a custom Linux kernel module) to use EPIT interrupts to wake up my system from WAIT mode. But power consumption in WAIT mode is still quite high for my purposes.
Thus, is there a wait to keep EPIT enable in STOP mode on the iMX6UL?
(According to the processor manual (CCM chapter), programming the CCGR1 register allows to keep EPIT clocks running only in run and WAIT mode. Similarly, setting the MOD_EN_OV_EPIT bit in CMEOR register doesn't seem to have any effect.)
Thanks in advance for any comment or advice,
解決済! 解決策の投稿を見る。
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Hello Igor,
Thanks for your answer. I forgot to state that I did set the STOPEN bit in the EPITx_CR register.
In the meantime, I found the answer to my problem: I configured the EPIT with the standard peripheral clock (putting 1 in CLKSRC field of EPITx_CR register), while this clock is disabled in STOP mode. I thus switched to the reference low-frequency clock (putting 3 in CLKSRC field of EPITx_CR register); this solved my problem, I can now use EPIT to wake up my system from STOP mode after a given delay.
Best regards,


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Hi Kévin
one can check bit STOPEN in register EPITx_CR and description in
sect.23.4.3.2 Low-Power Mode Behavior i.MX6UL Reference Manual
http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf
Best regards
igor
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Hello Igor,
Thanks for your answer. I forgot to state that I did set the STOPEN bit in the EPITx_CR register.
In the meantime, I found the answer to my problem: I configured the EPIT with the standard peripheral clock (putting 1 in CLKSRC field of EPITx_CR register), while this clock is disabled in STOP mode. I thus switched to the reference low-frequency clock (putting 3 in CLKSRC field of EPITx_CR register); this solved my problem, I can now use EPIT to wake up my system from STOP mode after a given delay.
Best regards,
