Imx8m-min Failed to replace 4GDDR. How do i configure the uboot

[gongyaxuan]

Our customer needs to use 4G DDR, I tried debugging, uboot and file system have shown 4G, but using memtester to test a little larger memory failed, I want to know how to configure 4G DDR properly, this is important to me

Attached is my configuration and chip manual

memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>,
<0x1 0x00000000 0 0x80000000>;
};

#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CONFIG_NR_DRAM_BANKS 2
#define PHYS_SDRAM_2 0xC0000000
+#define PHYS_SDRAM_2_SIZE 0x80000000

memory@40000000 {
device_type = "memory";
 reg = <0x0 0x40000000 0 0x80000000>,
 <0x1 0xC0000000 0 0x80000000>;
};

[gongyaxuan]

#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+#define PHYS_SDRAM_2 0xC0000000
+#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2GB */
+#define CONFIG_NR_DRAM_BANKS 2

[JorgeCas]

Hello,

 Is our board able to pass the DDR stress test?

How are you reading the addresses?

Best regards.

[gongyaxuan]

I am very glad to see your reply. I used imx config tool DDR configuration tool to configure according to the attachment "png" to pass the stress tests, and then replaced the timing.c file

uboot and file system display 4G, but the actual test failed, I think this may be because of the memory address and other gpu address conflict, can you tell me how to configure.

[JorgeCas]

Hello,

Please refer to section 4.5.1 Building u-boot image by toolchain command or 4.5.2 Building u-boot image under Yocto environment to do the integration.

Best regards.

[gongyaxuan]

Thank you for your reply,
1. I have replaced the timing file, although the uboot shows 4G, the actual test failed
2. Do you just need to change timing? Do optee and ATF need to be modified? This is where I am confused

[JorgeCas]

Hello,

Only timing and initialization files should be added to your build to use the selected values in DDR stress test to do the calibration.

Best regards.

[gongyaxuan]

Thank you for your reply,
1. I configured the DDR according to the manual and created the timing file and replaced it. At this time, the board started normally and uboot only displayed 2G
2. There are two DDRS on the board hardware when I modify include/configs/myd_imx8mm.h as follows
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+#define PHYS_SDRAM_2 0xC0000000
+#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2GB */
+#define CONFIG_NR_DRAM_BANKS 2 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+#define PHYS_SDRAM_2 0xC0000000
+#define PHYS_SDRAM_2_SIZE 0x8

After recompiling and starting, uboot displays 4G, but the kernel reports an error and cannot start.

U-Boot 2019.04-5.4.3-2.0.0+g081bb26f64 (Apr 09 2025 - 07:13:27 +0000)

CPU: Freescale i.MX8MMQ rev1.0 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C)CPU Temperature (46000C) has beyond alert (85000C), close to critical (95000C) at 46C
Reset cause: POR
Model: MYD i.MX8MM board
DRAM: 4 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... Run CMD11 1.8V switch
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial

BuildInfo:
- ATF f1a195b
- U-Boot 2019.04-5.4.3-2.0.0+g081bb26f64

Run CMD11 1.8V switch
switch to partitions #0, OK
mmc1 is current device
flash target is MMC:1
Run CMD11 1.8V switch
Net: Could not get PHY for FEC0: addr 4
Could not get PHY for FEC0: addr 4
eth-1: ethernet@30be0000
Fastboot: Normal
Normal Boot
Run CMD11 1.8V switch
switch to partitions #0, OK
mmc1 is current device
Run CMD11 1.8V switch
32954880 bytes read in 425 ms (73.9 MiB/s)
Booting from mmc ...
45089 bytes read in 6 ms (7.2 MiB/s)
## Flattened Device Tree blob at 43000000
Booting using the fdt blob at 0x43000000
Using Device Tree in place at 0000000043000000, end 000000004300e020

Starting kernel ...

[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[ 0.000000] Linux version 5.4.3-2.0.0+g7ee7bc4dc (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP PREEMPT Wed Apr 9 01:12:27 UTC 2025
[ 0.000000] Machine model: MYD-C8MMX-V2.0 i.MX8MM board
[ 0.000000] earlycon: ec_imx6q0 at MMIO 0x0000000030890000 (options '115200')
[ 0.000000] printk: bootconsole [ec_imx6q0] enabled
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: UEFI not found.
[ 0.000000] Reserved memory: created CMA memory pool at 0x0000000090000000, size 640 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] Internal error: synchronous external abort: 96000210 [#1] PREEMPT SMP
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.4.3-2.0.0+g7ee7bc4dc #1
[ 0.000000] Hardware name: MYD-C8MMX-V2.0 i.MX8MM board (DT)
[ 0.000000] pstate: 20000085 (nzCv daIf -PAN -UAO)
[ 0.000000] pc : __create_pgd_mapping+0x190/0x748
[ 0.000000] lr : __create_pgd_mapping+0x150/0x748
[ 0.000000] sp : ffff800011da3d60
[ 0.000000] x29: ffff800011da3d60 x28: ffff800010080000
[ 0.000000] x27: ffff800010080000 x26: fffffdfffe436800
[ 0.000000] x25: 00000000bdfbeaa0 x24: fffffdfffe437000
[ 0.000000] x23: ffff800010080000 x22: 0000000000000040
[ 0.000000] x21: 0000000000fc0000 x20: 0000000040480000
[ 0.000000] x19: ffff800040000000 x18: 0000000000000010
[ 0.000000] x17: 0000000000001400 x16: 0000000000001c00
[ 0.000000] x15: ffff800011db24f0 x14: ffffffffffffffff
[ 0.000000] x13: ffff800091da3ae7 x12: 0000000000000000
[ 0.000000] x11: 0000000000000004 x10: 0000000000000018
[ 0.000000] x9 : 0000000000000000 x8 : fffffdfffe43a000
[ 0.000000] x7 : 0000000000000000 x6 : 0000000000000000
[ 0.000000] x5 : ffff800011ff0000 x4 : 000fffffdfffe437
[ 0.000000] x3 : 0000000000000037 x2 : ffff80001103ffff
[ 0.000000] x1 : ffff80003fffffff x0 : 000000013ffff003
[ 0.000000] Call trace:
[ 0.000000] __create_pgd_mapping+0x190/0x748
[ 0.000000] map_kernel_segment+0x70/0xa4
[ 0.000000] paging_init+0x12c/0x5d0
[ 0.000000] setup_arch+0x268/0x5e8
[ 0.000000] start_kernel+0x88/0x44c
[ 0.000000] Code: f94053e2 92628673 d1000661 eb02003f (f9400301)
[ 0.000000] random: get_random_bytes called from print_oops_end_marker+0x28/0x50 with crng_init=0
[ 0.000000] ---[ end trace 0000000000000000 ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---

After recompiling and starting, uboot displays 4G, but the kernel reports an error and cannot start.

Could you please help me find out the reason for this? I will add my configuration picture to the attachment. Could you please help me check if there is any problem? I really need your help

[JorgeCas]

Hello,

You can refer to the method in patch.

If 8MM changed to 4GB size, it is need do changes in OPTEE side.

Best regards.

[gongyaxuan]

I look forward to your help. Please reply when you see the information. Thanks again

[JorgeCas]

Hello,

Yocto Project has by default OPTEE option and if are you not using OPTEE you can disable that feature and build again.

The OPTEE feature is configured to our EVK and probably is the reason that only detects 2GB.

You can disable OPTEE by OPTEE(MACHINE_FEATURES_remove = "optee").

Also, with modification of DDR size as is on patch, should work for your design.

Best regards. 

[gongyaxuan]

Thank you very much, this is indeed a solution. By turning off optee, the 4GDDR test is normal
I still want to ask if our customer needs optee, can you tell me how to correctly modify optee to fit 4GDDR
Thanks again for your help

[gongyaxuan]

Yes, I think optee needs to be modified. Can you tell me how to modify it
Another thing I'm confused about:
1. The patch you gave seems to only modify uboot, but not optee. Could you please confirm and tell me how to modify optee
2. I have read the patch content, and I don't quite understand why it is so set, but I will modify it according to this content and test it

Thank you for your help

+CONFIG_NR_DRAM_BANKS=3

+#ifdef CONFIG_IMX8M_4G_LPDDR4
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB */
+#define PHYS_SDRAM_2 0x100000000
+#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */
+#endif