Hi Igor,
There are 2 bits for each field, are there 4 values that can be assigned? The individual bits are not defined. What are the bits? Are they the same?
Table 18-3. System Clocks, Gating, and Override (continued)
Module Module Clock Clock Root Module Clock Gating Enable
IOMUXC IPT_CLK_IO LCDIF_PIX_CLK_ROOT CCGR2[CG7] (IOMUX_IPT_CLK_IO_ENABLE)
IOMUXC IPG_CLK_S IPG_CLK_ROOT CCGR4[CG1] (IOMUXC_CLK_ENABLE)
IOMUXC IPG_CLK_S IPG_CLK_ROOT CCGR4[CG2] (IOMUXC_GPR_CLK_ENABLE)
18.6.25 CCM Clock Gating Register 2 (CCM_CCGR2)
The figure below represents the CCM Clock Gating Register 2 (CCM_CCGR2). The clock gating registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR registers. The number of registers required is determined by the number of peripherals in the system.
Address: 20C_4000h base + 70h offset = 20C_4070h
BITS 15–14 CG7 iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable)
18.6.27 CCM Clock Gating Register 4 (CCM_CCGR4)
The figure below represents the CCM Clock Gating Register 4 (CCM_CCGR4). The clock gating Registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR registers. The number of registers required is determined by the number of peripherals in the system.
Address: 20C_4000h base + 78h offset = 20C_4078h ....
BITS 5–4 CG2 iomuxc gpr clock (iomuxc_gpr_clk_enable)
BITS 3–2 CG1 iomuxc clock (iomuxc_clk_enable)
