For 6.1.22 I'm using the following patch for the GIR-wakeup, just ignoring the unused defines from the original and wakeup is working fine.
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -260,7 +260,8 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
{
imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
priv->dcfg->xSR[IMX_MU_GSR]);
- mbox_chan_received_data(cp->chan, NULL);
+ if (cp->chan->cl)
+ mbox_chan_received_data(cp->chan, NULL);
return 0;
}
@@ -867,6 +868,18 @@ static int imx_mu_probe(struct platform_device *pdev)
return ret;
}
+ /* TY: Enable GIR wakeup { */
+ dev_info(dev, "enable wakeup GIE bit\n");
+ {
+ struct mbox_chan *chan;
+
+ /* TYPE: 3, Index: 0, 3 * 4 + 1 = 0 */
+ chan = &priv->mbox.chans[12];
+ chan->cl = NULL;
+ imx_mu_startup(chan);
+ }
+ /* } TY: Enable GIR wakeup */
+
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
--
And the following for the atf-m4-run:
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -20,7 +20,7 @@
#include <plat_imx8.h>
#include <imx_rdc.h>
-#define MAX_PLL_NUM U(10)
+#define MAX_PLL_NUM U(8)
static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };
@@ -316,8 +316,6 @@ struct pll_override pll[MAX_PLL_NUM] = {
{.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
{.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
{.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
- {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), },
- {.reg = 0x94, .override_mask = 0x5555500, },
{.reg = 0x104, .override_mask = 0x5555500, },
{.reg = 0x114, .override_mask = 0x500, },
};
--