M4 Low Power Demo on i.MX8MM

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M4 Low Power Demo on i.MX8MM

M4 Low Power Demo on i.MX8MM

Low power demo on i.MX8MM.

 

9/28/2020:

Attachments updated.

1. Fix a bug in 5.4.24 kernel that system can only wakeup once.

2. Remove 0x104 from atf patch. On 5.4.24, tested OK without PLL2.

 

9/8/2020:

Attachments updated.

Add patches for 5.4.24 kernel.

 

We use it to test power consumption on i.MX8MM EVK.

 

Usage:

1. Kernel:

echo "mem" > /sys/power/state

 

2. M4:

Select a power mode from menu and wait for wakeup.

Default wakeup method is GPT.

 

Add more patches, which will add functions for the case:

1. M core RUN and A core in suspend with DDR OFF.

2. M core wakeup A core without DDR support.

 

Descriptions:

1. freertos_hello.c.
A simple example for M4 RUN when A core in DSM. Generally, we use MU_TriggerInterrupts(MUB, kMU_GenInt0InterruptTrigger); to do wakeup.

 

2. atf patch:
Allow A53 to enter fast-wakeup stop when M4 RUN. Also avoid bypass of some plls, which is important to make M4 RUN when A53 enters suspend.

 

3. 0001-iMX8MM-GIR-wakeup.patch:
GIR wakeup patch for kernel. Need kernel to use
fsl-imx8mm-evk-m4.dtb.

 

4. 0002-Don-t-keep-root-clks-when-M4-is-ON.patch.
Don't keep root clocks when M4 is ON.

5. 0001-plat-imx8mm-keep-the-necessary-clock-enabled-for-rdc.patch.
There's a design issue that when wakeup from DSM, described in patch:

"

if NOC power down is enabled in DSM mode, when system resume

back, RDC need to reload the memory regions config into the

MRCs, so PCIE, DDR, GPU bus related clock must on to make

sure RDC MRCs can be successfully reloaded.

"

Note that this patch will keep PCIE, DDR and GPU clock on, which will increase the power.

A optimization will be decrease PCIE, DDR and GPU clock before entering DSM.

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hi terry_lr‌, i am trying to do the M4 wakeup A53 part. I understand that only patch "0001-iMX8MM-GIR-wakeup.patch" is needed for this. But i am on 5.4.24 kernel on my imx8mm, so looks like there are many changes and i dont see any irq/isr code there under imx_rpmsg.c.

Will you help to understand what i need to enable this functionality on 5.4.24 kernel on imx8mm. Also i suppose the other patches are not needed for M4 wakeup A53, am i right?

i am trying this on 4.14.98 kernel. I could not get the M4 wakeup A53 work on imx8mm. 

can you attach the  freertos_hello bin which needs to be loaded in M4 at u-boot for this demo? i understand this will work only with this freertos_hello bin, and not the pingpong or echo bin images

Hi Siva,

  The freertos_hello.bin is loaded at u-boot.

  The patch "0001-iMX8MM-GIR-wakeup.patch" need to work with ATF patches and freertos_hello binary.

  Normally, user should need 3 patches:

1. freertos_hello.c.  Use MU_TriggerInterrupts(MUB, kMU_GenInt0InterruptTrigger); to do wakeup.

 2. atf patch: Allow A53 to enter fast-wakeup stop when M4 RUN. Also avoid bypass of some plls, which is important to make M4 RUN when A53 enters suspend.

 3. 0001-iMX8MM-GIR-wakeup.patch: GIR wakeup patch for kernel. Need kernel to use fsl-imx8mm-evk-m4.dtb.

  Patch 4 is optional and this change won't have a big change in power.

  Patch 5 is for user that need to access RDC after wakeup.

  I've attached M4 binary. Please try it.

  Thanks!

Regards

Terry

hello Terry, 

Thanks a lot for the image and the details. It worked for me. (4.14)

Now i am wondering why the imx rpmsg driver changed a lot on 5.4 kernel where i am unable to correlate these patch changes, as before i tried on yocto imx zeus branch which is on 5.4.24. Do you have any idea about it?

Hi Siva,

  5.4.24 kernel is using mailbox. So

  1. Code in imx_mu_rpmsg_isr:
    +   } else {
    +       MU_ClearGIRInt(rpdev->mu_base, irqs & 0xf0000000);
    +       pr_err("MU GIR interrupt!\n");
    and
    +       MU_EnableGIRInt(rpdev->mu_base, 0x8);
    Can be moved to imx_mailbox.c proble function. This is just a reset of GIR.
  2. Function MU_ClearGIRInt and MU_EnableGIRInt can be put into imx_mailbox.c and changed to a proper name.

  Thanks!

Regards

Terry

Thanks, and how about the ATF patch?

Hi Siva,

  1. The patch
  2. The pll ctrl code on 5.4.24 should be in imx_anamix_override() now. See the function ./plat/imx/imx8m/gpc_common.c.
    So you should change:

    #define MAX_PLL_NUM 10

    struct pll_override pll[MAX_PLL_NUM] = {
    {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
    {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
    {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), },
    {.reg = 0x94, .override_mask = 0x5555500, },
    {.reg = 0x104, .override_mask = 0x5555500, },
    {.reg = 0x114, .override_mask = 0x500, },
    };
    to:

    #define MAX_PLL_NUM 7

    struct pll_override pll[MAX_PLL_NUM] = {
    {.reg = 0x0, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x14, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x28, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
    {.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
    {.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
    {.reg = 0x114, .override_mask = 0x500, },

  3. The SLPCR_A53_FASTWUP_STOP bit on 5.4.24 seems to be already set in imx_gpc_init() function. See code in ./plat/imx/imx8m/imx8mm/gpc.c.

  Sorry for the late reply. The new community seems not stable here and I can't reply yesterday.

   Thanks!

Regards

Terry

Hi Siva,

 

  The attachment is updated. Patches for 5.4.24 kernel is uploaded.

  Tested OK.

  Thanks!

Regard

Terry

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