IMX8QuadXPlus LPDDR4 CA SWAP in Channel

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 
已解决

IMX8QuadXPlus LPDDR4 CA SWAP in Channel

跳至解决方案
3,837 次查看
Wenhai_05
Contributor I

Dear

Could you confirm if there is any restriction of CA(Command & Address) swapping on LPDDR4?

Thanks!

BR

Alex

 

0 项奖励
回复
1 解答
3,828 次查看
Rita_Wang
NXP TechSupport
NXP TechSupport

Swapping of the CA lines is not supported.

在原帖中查看解决方案

0 项奖励
回复
3 回复数
3,833 次查看
Rita_Wang
NXP TechSupport
NXP TechSupport

As long as it complies with JEDEC specifications,no special. The details design you can refer to our hardware user guide document.

0 项奖励
回复
3,830 次查看
Wenhai_05
Contributor I

Dear

It is not stated in JEDEC specification. I think it depends on the features of DDR PHY and Controller.

As I know, IMX8QXP support data bus swapping. I can fill in my data configuration to get corresponding code. Refer to attachment, which is snapped in worksheet (BoardDataBusConfig) of  MX8QXP_C0_B0_LPDDR4_RPA_1.2GHz_V15.xlsx.

Similarly, due to layout, I have the requirement of CA swapping. Such as, DDR_DCF00 is configured to CA2_A, I want to configure it as CA5_A.

There are not these information in user guide .

Thanks!

BR

Alex

0 项奖励
回复
3,829 次查看
Rita_Wang
NXP TechSupport
NXP TechSupport

Swapping of the CA lines is not supported.

0 项奖励
回复