IMX8MP eMMC IOMUX issues

[petertseng]

Hi

Our customer's IMX8MP board replaced the eMMC IOMUX pins.

&usdhc3 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	assigned-clock-rates = <400000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&iomuxc {
	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK		0x190
			MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD		0x1d0
			MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0	0x1d0
			MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1		0x1d0
			MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2	0x1d0
			MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3		0x1d0
			MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4		0x1d0
			MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5	0x1d0
			MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6		0x1d0
			MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7		0x1d0
			MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE	0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK		0x194
			MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD		0x1d4
			MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0	0x1d4
			MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1		0x1d4
			MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2	0x1d4
			MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3		0x1d4
			MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4		0x1d4
			MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5	0x1d4
			MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6		0x1d4
			MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7		0x1d4
			MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE	0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK		0x196
			MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD		0x1d6
			MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0	0x1d6
			MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1		0x1d6
			MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2	0x1d6
			MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3		0x1d6
			MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4		0x1d6
			MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5	0x1d6
			MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6		0x1d6
			MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7		0x1d6
			MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE	0x196
		>;
	};
};

But the clock is still measured on the NAND_WE_B pin.

Please help me in resolving this error

Thanks in advance,

Best Regards
Peter

[Zhiming_Liu]

Hi @petertseng 

Does customer comment the iomux about NAND_WE_B ?

Best Regards

Zhiming

[petertseng]

Hi Zhiming,

The customer specifies NAND_WE_B as a general GPIO.

Best Regards
Peter

[Zhiming_Liu]

Hi @petertseng 

Can customer share their device tree file?

Best Regards

Zhiming

[petertseng]

Hi Zhiming,

MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x194

Best Regards
Peter

[Zhiming_Liu]

Hi @petertseng 

Customer can try pinctrl value: 0x16

[petertseng]

Hi Zhiming,

Is that what you mean?

MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x16

Best Regards
Peter

[Zhiming_Liu]

Hi @petertseng 
Yes.

Best Regards
Zhiming

[petertseng]

Hi Zhiming,

I think you misunderstood me.

What I want is to connect the eMMC (uSDHC3) to the Ethernet pin (ENET) of the IMX8MP.

And hope to boot from eMMC.

But it seems that IMX8MP cannot do this:

https://community.nxp.com/t5/i-MX-Processors/IMX8MP-Boot-from-eMMC-at-Ethernet-Port/m-p/1295356#M175...

Thank you very much for your reply.

Best Regards
Peter

[Zhiming_Liu · Accepted solution]

Hi @petertseng 

Yes, the behavior of bootrom is fixed, we can't let it boot from ENET pins. The usdhc3 clock can only from NAND_WE_B.alt2 when boot.

Best Regards
Zhiming