IMX6UL layout

[kaveeh]

Hi,

It seems that in the Layout of IMX6UL 9x9 evk board, the group of the high-speed signals (Data B0, B1 and Addr) are not routed on the same layer which is not suggested by the hardware design guide. Is the possible to follow the evk board design and routing the bus group in the different layers since imx6ul run at lower frequencies compare to the imx6s or imx6q families?

And where we can find the init scrip file for LPDDR2 stress test?

Thanks,

[igorpadykov]

Hi kaven

in general bus group can be routed in the different layers, recommended to

use ibis modelling. Regarding scripts one can look at

i.MX6/7 DDR Stress Test Tool V2.40

Best regards

igor

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[kaveeh]

Hi Igor,

Thanks for your reply but there is a misunderstanding about my question. Certainly we can not route all the buses in one layer but my point relates to each group. For each group, we need to route in one layer or, at least, respect the same topology if we want to switch the layer. However, this is not the case in the 9x9 evk board. For instance, you will find that the DRAM_DATA 11 is routed on top layer while the DRAM_DATA 10 is routed on the inner layer which will not have the same impedance properties in the stack-up.

Best 

[igorpadykov]

Hi kaven

in general it is recommended to follow User Guide

guidelines, however based on ibis modelling one can use

other topology.

Best regards

igor