IMX6UL DDR Test tool Stress Test

[alubeiro]

Hi all,

I have a customized board based on a IMX6UL with the DDR3 ref MT41K64M16TW-107 from Micron.

Our script file is modified from the one of the MCIMX6UL-EVK. PLease find it attached.

The fact is that when i try to pass a Stress test it always fail at ADDR 0x80002100 and when i hit it again it increases the ADDR failed in blocks of 0x40 like 0x80002140, 0x80002180 etc...

I have also made this test:

1- Download the script.

1- Read 32 words from 0x87003000. They are rubish.

2- Try a stress tess. It fails at address 0x80002100

3- Read again 32 words from 0x87003000. Atonishly they are correctly written.

How does this tool work? does it write the whole memory despite the stress test fails for example in addr 0x80002100 and at the end it shows the addr in which the test has failed? it looks like it does.

Thanks and best regards

[alubeiro]

Hi guys,

One last thing.

I made some coparisons between the board that doesn't work and the other 3 that they do and what i saw is the following.

     - 1. As you can see in the pictures above, the CLK_P signal must change from high to low when the script is loaded and after some time, it realises to high again. (the low level is 0.650 mV which is VRAM/2).

The board which doesn't work keeps low.

     - 2. The SDQS signlas must be low (0V) until the stress test is lunched. Then, they must reach the 0.65mV (VRAM/2) and keep there until the end of the proccess when they realise to Low (0V) again.

At the board which doesn't work, these signals go to VRAM/2 (high) at the same time the script is loaded and they keep there.

If i try a stresst test, it fails.

We don't know what else can we check, so we are going to send the board to be analysed by x-rays so we can figure out if there is any shortcircuit in BGA's solder joints.

The fact that all these is happening at the moment of dowloading the script, make us belive maybe there is a problem in any BGA pad.

I will post here the results.

PD: If anyone makes any progress, please post it here.

Thanks and best regards.

[fernandotengelm]

Hi guys,

Good news my board is working checking all clock signals one of their was missing after re check schematic we send the board to a x-ray check and some pads was not soldered after the fix all is working.

Thank you all.

[fernandotengelm]

Hi guys,

My board still not running the callibration and the stress test but I can R/W manually any address.

What was the software used to build your board? To reduce the chance of errors on memory bus we tryed to import the NXP Allegro board project into Altium but was not possible, the import process returns ok but the board is out of the range of the work space.

Regards.

[alubeiro]

Hi again,

I forgot to attach a couple of captures.

They are captures of signal "DRAM_SDCLK0_P" just at the moment of downloading the script with the DDR Test Tool

This one beyongs to a board which is working fine.

This one beyongs to the one which does not pass stress test but is it posible to do single W/R.

The "DRAM_SDCLK0_N" signal has the same behavior but upside down.

Any idea, will be apreciated.

Thanks

[fernandotengelm]

Hello, everybody.

We are also working with the iMX6UL,We made our own board based on EVK design but we didn't use the nxp files because the import to Altium failed, so the EVK design was just a reference.

In our case during the stress test we had the same issue reported by Mr. Alberto, the board is following all manual recomendations, we are in the 3rd revision and the issue is the same.

Somebody have a tip to help?

[alubeiro]

Hi Jiri,

Firts of all, thanks for your response.

I still don't understand one thing. how did you achieve to burn the nand, if it does not pass the stress test?

We use the MFGTool to do so, and we have noticed that if the board does not pass the stress test at 400Mhz it does not pass the burn proccess either with MFGTool.

Did you place a nand already burned o do you use another way to burn the nand?

As for our design, we also had our boards with design based on EVK and we also made a rerouted correcting a lot of tracks lenghts in order to be in recommended length difference limits.

After this new rerouted is when we are having this issue with this board (does not pass the stress test but it can be made single w/r). We have other 3 working succsessfully

Thanks and best regards

[jiriluznicky]

I still don't understand one thing. how did you achieve to burn the nand, if it does not pass the stress test?

Because our board fully works when "cold started". So I can use MFG Tool as usual. I actually noticed the problem with stress test after few hours during u-boot tuning as the board stops working. First of all, I suspected bad u-boot configuration. Later I found the problem with stress test and strange behavior when power is removed.

[fuse]

Hi Alberto, Yuri

I'm facing the same issues and behaviour with the stress tool, on our custom board.

We use a DDR3LV Micron MT41K128M16JT-125 and the init script seems to be ok.

No issues with JTAG single memory access and the "MX6 DRAM Bus Length Check" seems to be ok .

On the iMX6UL - EVK we're able to force the same failure editing the init script .

Are there any hints about the DDR3 Stress tool?

Thanks in advance

Regards,

Riccardo

[alubeiro]

Hi Riccardo,

In our case we also could make single memory access, finally we decided to make a new design chanching the layout because we didn't make good grounds planes and now the stress test and calibration are made successfully, so check your PCB design.

I guess that your script file is good if you have access to DDR.

[fuse]

Hi Alberto,

bad news from your side... Before making a new pcb we'll investigate again to the script file; I hope to find the problem there (but I'm not confident).

Thanks for your help.

Best Regards

Riccardo

[jiriluznicky]

Hi all,

we're facing the same problem. We have two same boards with design based on EVK. One of these boards works fine. The second one boots sometimes. We also tried two different memory. One from Micron, other from ISSI on the same board with no change in behavior.

Behavior of the board in stress test is always absolutely same as described by Alberto.

We will be glad for any hint about PCB resigned, or if someone knows what exactly leads to this behavior in stress test.

Thanks and best regards

Jiri

[alubeiro]

Hi Jiri,

When you say "The second one boots sometimes" do you mean that it passes stress test sometimes? Because for booting, the RAM must be burned first and this can't be done if it is not able even of passing the stress test.

At this moment we got two same boards too, one pass the stress test successfully, RAM can be burned and all harware is working fine, like ethernet, wifi etc... but the other one does not pass the stress test even at the lowest speed. I must say the RAM configuration script is loaded successfully and that single writes and reads can be made either by JTAG or by DDR Test Tool.

In anyway, i have checked the power supplies, all solder joints of the decoupled capacitors and resistors which are part of the RAM circuit and they all seem to be ok.

A couple of doubts:

     -     Don't you think that R206 of EVK schematic"470 ohm" is too high? In many other designs this resistor is much lower

     -     What about R207 and R208? they are 1% and it is supposed that DRAM_VREF must be under 1% of the half of DRAN_1V35

By the way, have you made any progress with your second board? Maybe it can give us any clue.

Any help will be apreciated.

Thanks and best regards

[jiriluznicky]

Hi,

the behavior of "the second one" is a bit tricky. If you connect power to the board then it works perfectly. It boots from NAND (u-boot, Linux) and runs flawlessly for hours. You can even reset it. But if you disconnect power, then it stops working and you have to wait  5 - 10 minutes till it starts working again.

Behavior in DDR tool is always same despite of the state. Stress test fails, single r/w works.

Because we weren't able to do any progress, we decided to reroute a board bit as we were on edge for example on diff. clocks and DQS pair where we were almost on recommended length difference limits. Now we're waiting for new boards.

[Yuri]

Hello,

  Some details about tests may be found at i.MX53 - LPDDR2 DDR Stress Test

Have a great day,
Yuri

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[alubeiro]

Hello Yuri,

First of all, thanks for your quick response.

Sorry but I did not get anything of the link you posted. I am trying it with DDR Test Tool v2.40

So please,  could you check the the device information in script and tell me if it is ok?

As for the way a stress test is done, am i right in the above suggestion?

Thanks and best regards.

Have a great day you too.

[Yuri · Accepted solution]

Hello,

   I do not see obvious bugs in Your memory configuration. 

As for for the way the stress test is done - You are  right regarding the above suggestion.

Please try to check Your PCB design, using "MX6 DRAM Bus Length Check" sheet

in the following i.MX6 Design Checklist.  

https://community.freescale.com/docs/DOC-129659

Regards,

Yuri.

[alubeiro]

Hi Yuri,

One question about the strees test process.

you said I was right when i said that during a stress test, the whole memory is written despite the test fails for example in addr 0x80002100. It ends the test and then it shows the addr in which the test has failed, right?

I am a bit confused because the following:

In step 3 of my first post, this bunch of addresses (0x87003000) are only correctly written as long as i read them first, before running the stress test, otherwise they are rubish.

Why is this?

Thanks and best regards

[Yuri]

Hello,

  Please try the following :

1. Run the stress test calibration.

2. Change DRAM initialization script, using optimal data of the previous calibration.

3. Run the test again with new script.

Regards,

Yuri.