Hi Igor,
Thank you for the clarifications. That was my understanding as well and that's why I did a test where the frames decoded by VPU are simply dropped and not displayed. I expected the bus load to drop and to see the VPU getting enough bandwidth to do whatever it is doing. I expected the average write burst to become close to 64 in this case, like in 4.3.
Surprisingly, what I see in this case is that, although the bus load does drop significantly (down to 76%) and the VPU gets its share of the bandwidth (590.57MB/s, close to what it uses up in 4.3), the average write burst size still remains 16!
These are the measurements:
MMDC VPU
***********************
Measure time: 500ms
Total cycles count: 264044584
Busy cycles count: 201964997
Read accesses count: 6833583
Write accesses count: 6065570
Read bytes count: 209241968
Write bytes count: 100384432
Avg. Read burst size: 30
Avg. Write burst size: 16
Read: 399.10 MB/s / Write: 191.47 MB/s Total: 590.57 MB/s
Utilization: 9%
Overall Bus Load: 76%
Bytes Access: 24
MMDC SUM
***********************
Measure time: 500ms
Total cycles count: 264044512
Busy cycles count: 200866383
Read accesses count: 10714476
Write accesses count: 6085360
Read bytes count: 458671512
Write bytes count: 101112032
Avg. Read burst size: 42
Avg. Write burst size: 16
Read: 874.85 MB/s / Write: 192.86 MB/s Total: 1067.70 MB/s
Utilization: 17%
Overall Bus Load: 76%
Bytes Access: 33
So it seems that no matter how I make VPU's life easier it never goes above 16 byte write bursts, in contrast with the 4.3.
Do you have any idea why this is happening?
Best regards,
Stan