IMX536 current requirement failure & Power on sequence query

[neerajshukla]

Hello,

We are designing a board for industrial application with maximum temperature of 85C, based on  IMX536 processor in our design with PMIC 34709.

But there is a problem regarding current requirement, VGEN2(2.5V) Rail of PMIC is connected to  VDD_REG of IMX53.

The current required by IMX53's VDD_REG rail [it powers  VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) also] is 325mA and current provided by PMIC's VGEN2 rail 250mA which is less,

• How is it possible?

So,we are  powering  VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V) externally from VUSB2 LDO(2.5V) of PMIC, is it possible to do so? This has not been implemented any where.

• Will it affect USB usage in our case as we are planning to use USB also ?

• Is there any power up sequence required for rails "VDD_ANA_PLL(1.8V) and VDD_DIG_PLL(1.3V)" ?

[reyes]

1. VDD_REG 325mA in Table 9 "Maximal Supply Currents" of the i.MX53 Datasheet (IMX53AEC, Rev. 5, 12/2012) is given for the worst conditions, assuming VDDA and VDDAL1 are driven by the VDD_DIG_PLL (produced from VDD_REG). Please refer to footnote 4 to Table 7 "i.MX53xA Operating Ranges": "VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections."

Let me remind, according to section 4.9 (Integrated LDO Voltage Regulators Parameters): "The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1."

So max. VDD_REG 325 mA includes at least VDDA + VDDAL1 max.100mA.

On i.MX53 QSB schematic (with the PMIC 34708) VDDA + VDDAL1 are not connected to VDD_DIG_PLL (and not consumes max.100mA from VDD_REG), they are connected to VGEN1. For such connection VDD_REG max current consumption may be estimated as (325mA - 100mA) = 225mA, sufficient for VGEN2 of PMIC 34708.

Please note that Table 9 "Maximal Supply Currents" gives max. currents for worst conditions, typical values are less. For VDD_REG typical current please refer to application note AN4271 (Rev. 0, 7/2011) "i.MX53 Supply Current Measurements on MCIMX53SMD Board"

< http://www.freescale.com/files/32bit/doc/app_note/AN4270.pdf >

2. Recommended power supply solutions may be found in Chapter 5 (Setup Power Management) of “i.MX53 System Development User’s Guide”. Please pay attention on erratum ERR007080 (LDO: On-chip LDO regulators may not enable or have a delayed output on power up).

< http://cache.freescale.com/files/32bit/doc/errata/IMX53CE.pdf >

VDD_ANA_PLL and VDD_DIG_PLL may be powered externally (with proper voltages).

As for power up sequence please take a look at section 4.2.1 (Power-Up Sequence) of the Datasheet: “If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage during the power-up, it is recommended to activate the VDD_REG before or at the same time with VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V VDD_REG supply shut-off output impedance is higher than 1 kOhm when it is inactive.”