I2C interrupt request

[adityanagal]

Hi ,

In the reference manual , table 3-1 , IRQ no 67 to 69 are for I2C devices . My question is , in case of I2C , CPU itself is the master and generates the clock for the slave device . All I2C transactions are initated by the I2C master only , then how come slave device will give the interrupt to the CPU . Please advice.

Regards,

Aditya Nagal

[igorpadykov]

Hi Adytia

according to sect.36.7.4 I2C Status Register (I2Cx_I2SR)  i.MX6SDL RM

http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SDLRM.pdf 

The interrupt is set when one of the following occurs:
• One byte transfer is completed (the interrupt is set at the falling edge of the ninth clock).
• An address is received that matches its own specific address in Slave Receive mode.
• Arbitration is lost.

Best regards
igor
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