Hi,
i am working on custom board with Imx RT1176 microcontroller onboard. I am trying to establish communication between cores. My goal is for both cores to be able to read and write in shared memory. IDE is Keil, debugger Ulink2.
I started from SDK example MU communication with interrupt. It works fine.
I have read AN13264 and tried using shared memory to write from M7 and from M4.
When i use CM4 DTCM I can write and read from both cores, but when I try to write to OCRAM only M7 core can write. I can read the data from M4 side, but I cannot write.
I tried disabling bus cache like this thread posted:
https://community.nxp.com/t5/i-MX-Processors/Cortex-M4-bare-metal-application-cannot-read-data-from-...
but nothing changes.
What could be the reasons M4 core cannot write to OCRAM part of the shared memory?
Any help is appreciated,
Best Regards,
Milan.