RMII reference clock to PHY on i.mx93 (ENET_FEC)

[etostd]

I have a custom board with a imx93 processor (SiliconRev2.0) where we have connected a PHY in RMII mode where the imx93 shall generate a 50MHz clock at MX93_PAD_ENET2_TD2__ENET1_TX_CLK.

The problem is that there are no clock output at all.

We have followed AN14149 'Ethernet Controller Configuration on i.MX 8MP and i.MX 93 Processors' (Rev. 1 — 8 January 2024) chapter 4.3.1 'ENET FEC interface configuration => RMII mode'

Can there be issues related to the new silicon or may there be issues missed out in the application note?

I am reaching out to the forum to get any information that can help us progress in this issue.

Attached follows patched version of fec_main.c with some extra printouts that shows that the code actually to the line where CLK_SEL is written.

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Seems like the changes from App Note are applied,

Could you confirmed if you probed the ENET2_TD2 pad and saw no clock output at all?

Regards