RMII reference clock to PHY on i.mx93 (ENET_FEC)

[etostd]

I have a custom board with a imx93 processor (SiliconRev2.0) where we have connected a PHY in RMII mode where the imx93 shall generate a 50MHz clock at MX93_PAD_ENET2_TD2__ENET1_TX_CLK.

The problem is that there are no clock output at all.

We have followed AN14149 'Ethernet Controller Configuration on i.MX 8MP and i.MX 93 Processors' (Rev. 1 — 8 January 2024) chapter 4.3.1 'ENET FEC interface configuration => RMII mode'

Can there be issues related to the new silicon or may there be issues missed out in the application note?

I am reaching out to the forum to get any information that can help us progress in this issue.

Attached follows patched version of fec_main.c with some extra printouts that shows that the code actually to the line where CLK_SEL is written.

[etostd]

Hi,
I have now made two new tests.
1) I tried to run the code on an IMX93 EVAL-KIT with A1-mask processor
   => There is no clock output on the ENET2_TD2 on the eval kit.
        This may indicate that the problem is the same for A1-mask hence easier to reproduce using standard HW.

2) I tried to change the DTS-file to set up ENET2_TD2 as gpio4.17
     Then I toggled the pin using 'gpioset'-command.
     => The pin was possible to control using 'gpioset'.
      This is a varification of the signal path from DTS to physical pin, and that there is no short-circuit in the custom layout.

Based on the outcome of these tests I think we should look inside IMX93 at the setup of clocks.
Is the clock set-up correctly?
It the clock enabled?
Are there error conditions that can disable the clock?

Best regards

[etostd]

Hi,

We have now been able to solve our clock problem.

The problem was twofold:

1) Measurement problem - the scope used were set up with BW-limitation.

BW-limitation reduced the 50MHz square wave (3v3) to a 50MHz sine wave (400mvPP)

2) The setup described in AN14149 was not correct.

It stated that the assigned clock rates should be: assigned-clock-rates = <100000000>, <100000000>, <50000000>;

This resulted in a 100MHz clock rate that occured as DC 1v8 when measured with BW-limitation.

The solution was to change the assigned clock rates to be: assigned-clock-rates = <100000000>, <50000000>, <50000000>;

This resulted in a 50MHz clock rate.

Please update AN14149

[JosephAtNXP]

Hi,

Could you try to remove the second occurrence of "fsl,imx8mp-fec" in your DTS and then share the dmesg, there is probably useful information.

From our side we haven't got such case from the internal tests nor customers, since you have confirmed that it's the correct ball and it's not tied, probably there is an error.

Regards,

[etostd]

This can not be the case.
The fec_main.c does not match "fsl,imx8mp-fec", it has the following compatible:
static const struct of_device_id fec_dt_ids[] = {
{ .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
{ .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
{ .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
{ .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
{ .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
{ .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
{ .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
{ .compatible = "fsl,imx8mq-fec", .data = &fec_devtype[IMX8MQ_FEC], },
{ .compatible = "fsl,imx8qm-fec", .data = &fec_devtype[IMX8QM_FEC], },
{ .compatible = "fsl,s32v234-fec", .data = &fec_devtype[S32V234_FEC], },
{ /* sentinel */ }
};

[JosephAtNXP]

Hi,

fec_main.c is getting merged by imx8mq, but imx8mp was repeated in your code.

I'd recommend to review the patching, customers cannot replicate.

Are you able to replicate on EVK?

Regards,

[etostd]

I will try to remove the repeated compatible string in DTS.

I have tried to replicate on EVK, but the EVK is using RGMII.
If the driver finds a mismatch, the clock is automatically disabled.

[JosephAtNXP]

Hi,

Thank you for your interest in NXP Semiconductor products,

Seems like the changes from App Note are applied,

Could you confirmed if you probed the ENET2_TD2 pad and saw no clock output at all?

Regards

[etostd]

Yes I measured with oscilloscope at two boards, and there were 0V and no activity.

[JosephAtNXP]

Hi,

Ok, let me review it.

Regards