Howto make unused ethernet controller less noisy

[lom]

Hi

We are using a Variscite DART-6UL SOM (MCIMX6G2 proc) placed on a custom board. As build environment buildroot is used. The SOM has one PHY (KSZ8081) populated on the first ethernet lines. This is the ethernet line we use, balls belonging to 2nd ethernet controller are used as uarts, digital io's, chip select signals and so on.

We ran into troubles with radiated emission measurements, seeing spike @ 200 and 300 MHz exceeding the limits by far (over 10dB). We did following investigations:

• When disabling both fec in the device tree, these spikes disapear. Only disabling the 2nd: spikes are here. So we really think it cames from the ethernet controller and/or it's clocks.
• Using an E-Field probe we saw that lines emitting most are belonging to the 2nd ethernet controller.
• When setting pins belonging to 2nd ethernet as outputs in the hog section and disabling uart, etc.. functionality, spikes are still there.
• We of course also added caps on some lines, reducing the radiation slightly. We will do some more tests trying to  place caps on every line belonging to 2nd ethernet. It's however - if it works - quit an ugly solution.

Is there a way to stop this coupling out by software? For now we only "disabled" fec2 in the device tree. Are there way's to stop that more explicitly, or at least to lower the harmonics going out? The Variscite support seems also be reaching its limit, so any advise, input or suggestion is highly appreciated

Thanks in advance

Louis

[igorpadykov]

Hi Louis

seems most simple is to disable enet clock using CCM_CCGR3(CG2) register.

With software changes for fec2 one can try to change IOMUXC_GPR_GPR1 (ENET2_CLK_SEL,ENET2_TX_CLK_DIR).

Best regards
igor
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[lom]

Hi Igor

thanks a lot for your response. I changed the settings with devmem on GPR1 register. It turned out that the noise isn't coming from fec2, but is coupling out from ENET1_TX_CLK. By setting the IOMUX pad to a higher output resistance we can reduce emissions by about 15dB, with even not too ugly clock signal. I'll check with the SOM support for correct solution.

Best regards

Louis