How to use the DDR3L for i.MX8M

[wawe]

Hi,

I designed a board with imx8m and 2 chips of DDR3L, part number is mt41k256m16tw-125 AAT, which could not be calibrated with MSCALE_DDR_Tool.
I used two CS signals and two CLK signals, CS0 and CLKA(CLKA_N/CLKA_P) for one DDR3L, CS1 and CLKB(CLKB_N/CLKB_P) for anohter DDR3L。
My question is how to set the MSCALE_DDR_Tool to pass the calibration? And if electrical connection is correct? The following PDF file is part of my schemtic for your reference.

Thank you.

[ameliaclarkson2]

thanks for sharing Kroger Feedback

[wawe]

Hi igor，

I received the email, I still have a question about the connection of the ddr3, if imx8m connects two chips of ddr3 use two CS signals, whether the two chips of DDR3 must be connected to the low 16-bit data line? Is not imx8m's DDRC a dual channel controller?  

Best regards.

[igorpadykov]

Hi WEI

your connections also can be used.

Best regards
igor
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[wawe]

Hi igor,

    How can I set the "MX8M_DDR3L_RPA_v6.xlsx" file ,I tried so many times,but always fail. The follow pitcure1（16bit data width,two CS）and pitcure3（32bit data width,two CS） are my configuration, picture2 and picture4 are the DDR TOOL calibration resualt.

   

                                                              PICTURE1

                                             PICTURE2

                                              PICTURE3

                                              PICTURE4

Finally, I found when configure one CS signal ,that is to say enable one ddr3 only, the calibration get passed. The following  is  screenshot.

I want to know how to configure the parameters to make two ddr3 chips work.Could you give me the direction?

Thank you for help.

Best regards.

[igorpadykov]

Hi WEI

one can follow Chapter 4 How to bring up a new MX8MSCALE board MSCALE_DDR_Tool_User_Guide.pdf
included in ddr test package

i.MX8 MSCALE SERIES DDR Tool Release (V2.10) 

also example of ddr3l connections were sent via mail.

Best regards
igor
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