I want to know the optimizations such as
Apply clock gating whenever clocks or modules are not used, by configuring CCGR registers in
the CCM (Clock Controller Module).
Reduce the number of operating PLLs—Applicable mainly in Audio Playback mode or Idle
modes.
DDR interface optimization:
...........
Are these optimizations contained in the current bsp or not? If not ,can we do the job by ourself?