How to force i.MX8 MQuad PCIe into Gen1 mode

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How to force i.MX8 MQuad PCIe into Gen1 mode

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Kawahata
Contributor II

Hi,

I am using i.MX8 MQuad board "NXP MCIMX8M-EVKB".
It normally runs PCIe Gen2, but I want to run it PCIe Gen1 for more stability.
Could you please teach me how to set PCIe max-speed to Gen1 in the devicetree or kernel-source, or how to set register after starting the kernel ?

I tried the following modifications, but it seems ineffective.

[linux kernel 4.14.78 with ubuntu16.04 LTS]
* arch/arm64/boot/dts/freescale/fsl-imx8mq.dtsi
Change "fsl,max-link-speed = <2>" to "fsl,max-link-speed = <1>".
--> It seems ineffective.
* driver/pci/pci.c
Set "next_speed = PCIE_SPEED_2_5_GT".
--> It seems ineffective.
* driver/pci/probe.c
Set "PCIE_SPEED_2_5_GT" for pcie_link_speed[].
Set "bus->max_bus_speed = PCIE_SPEED_2_5_GT".
--> It seems ineffective.

About i.MX6 it was found the following cases, but I want to know information about i.MX8 MQuad.

How to force iMX6 PCIe into Gen 1 mode @ imx_4.9.88_2.0.0_ga
https://community.nxp.com/t5/i-MX-Processors/How-to-force-iMX6-PCIe-into-Gen-1-mode-imx-4-9-88-2-0-0...
How to force iMX6 PCIe into Gen 1 mode
https://community.nxp.com/t5/i-MX-Processors/How-to-force-iMX6-PCIe-into-Gen-1-mode/m-p/264957#M2738...

Best Regards,
Kawahata

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4,433件の閲覧回数
Kawahata
Contributor II

Hi igor

Thank you for your support resolving the PCIe Gen1 setting in i.MX8 environment.
I modified the source based on the patch, and I have succeeded in getting Gen1 operation (2.5GHz) with the lspci -vvv command.
I’m grateful for your help.

Best Regard,
Kawahata

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4,434件の閲覧回数
Kawahata
Contributor II

Hi igor

Thank you for your support resolving the PCIe Gen1 setting in i.MX8 environment.
I modified the source based on the patch, and I have succeeded in getting Gen1 operation (2.5GHz) with the lspci -vvv command.
I’m grateful for your help.

Best Regard,
Kawahata

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Kawahata
Contributor II

Hi igor

>> Try use lspci -vvv?

Yes, it is shown "5GT/s".
If this information is correct, it has a PCIe Gen2 connection.
* LnkCap: Port #0, Speed 8GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <64us
* LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

I checked devicetree binary by following command, and it was written "fsl,max-link-speed = <1>".
---> dtc -I dtb -O dts -o fsl-imx8mq-evk.dts fsl-imx8mq-evk.dtb

I understand the specification that even if PCIe connects with Gen2, it will automatically change to Gen1 if the communication status is bad.
However, I don't understand why the result of lspci-vvv is Gen2 even though I specified "fsl,max-link-speed = <1>".
Is there any other setting required for Gen1 operation.

Best Regards,
Kawahata

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igorpadykov
NXP Employee
NXP Employee

from team:

---------------------

Reference the patch.

Reason: The Link speed data cannot write into PCIE_RC_LCR register.

11.3.3.1.27 Link Capabilities Register. (LINK_CAPABILITIES_REG) 

 

8MQ is support two PCIE,  Modify the speed of the corresponding interface in

the device tree.

---------------------

Best regards
igor

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Kawahata
Contributor II

Hi igor,

Thank you very mush for your reply.
I'm debugging the pci source, but it's recognized as Gen2 with the lspci -vv command.
How can I limit PCIe and fix it to Gen1 ?
(* I can't use any other kernel version because the external WLAN chip driver specifies kernel 4.14.78.)

About fsl-imx8mq.dtsi, whether max-link-speed is <2> or <1>, the result of "lspi -vv" is always Gen2.

Next, I checked how to judge Gen1 or Gen2 when starting kernel.
In pci-imx6.c, Link up GenX is calculated from the following values ​​by the formula "(value >> 16) & 0xf".

imx6q-pcie 33c00000.pcie: *** [PCIE_RC_LCR ]: Link up, Gen1 (0x0071CC12)
imx6q-pcie 33c00000.pcie: *** [PCIE_RC_LCSR]: Link up, Gen2 (0x30120000)

PCIE_RC_LCR  : (0x007 '1' CC12) --> Gen'1'
PCIE_RC_LCSR: (0x301 '2' 0000) --> Gen'2'

About PCIE_RC_LCR, any value can be written, but it does not affect the result of lspci -vv.
About PCIE_RC_LCSR, I thought I could make it Gen1 by writing (0x301 '1 '0000), but it seems it can't edit.
The value of PCIE_RC_LCSR (0x30120000) is fixed when pci_imx_ltssm_enable() is executed in imx_pcie_establish_link().
I don't know how to launch it as Gen1 here.

Best Regards,
Kawahata

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igorpadykov
NXP Employee
NXP Employee

below answer from internal team:

--------------

should Change "fsl,max-link-speed = <2>" to "fsl,max-link-speed = <1>".

why you think ineffective?

Try use lspci -vvv?

--------------

Best regards
igor

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igorpadykov
NXP Employee
NXP Employee

Hi Kawahata

 

according to nxp official document  i.MX Linux Reference Manual​  and sect.4.8.6 PCIe Driver Source Files i.MX8 MQuad PCIe uses the same driver as i.MX6, also driver has dts property " max-link-speed", line 2687

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/pci/controller/dwc/pci-imx6.c?h=lf...

So it should work as for i.MX6 case. May be recommended to try with latest nxp official nxp releases

from source.codeaurora.org/external/imx/linux-imx repository
https://source.codeaurora.org/external/imx/linux-imx/tree/?h=lf-5.10.y

Documentation

https://www.nxp.com/design/software/embedded-software/i-mx-software/embedded-linux-for-i-mx-applicat...

 

Best regards
igor

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