How to force iMX6 PCIe into Gen 1 mode

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How to force iMX6 PCIe into Gen 1 mode

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Contributor II

I am evaluating the Sabre SD board with a PCIe switch, and I am having issues getting it to work in Gen 2 mode.

This is using the Linux kernel 3.0.35-4.0.0 BSP.

I would like to force it into Gen 1 mode for testing, and this patch has worked to get it going for initial bring up.

===========================================================================

--- patched-linux-3.0.35-imx/arch/arm/mach-mx6/pcie.c   2013-09-26 14:49:46.000000000 -0700

+++ linux-3.0.35-imx/arch/arm/mach-mx6/pcie.c   2013-09-26 15:37:49.720701981 -0700

@@ -1021,8 +1021,13 @@ static int __devinit imx_pcie_pltfm_prob

        if (!(pdata->type_ep)) {

                /*Only RC: togle the external card's reset */

                card_reset(dev) ;

+               usleep_range(4000, 5000);

                imx_pcie_regions_setup(dev, dbi_base);

+               usleep_range(4000, 5000);

+                /* Force GEN1 */

+                writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1), dbi_base + LNK_CAP);

+               usleep_range(4000, 5000);

        }

        pr_info("PCIE: %s start link up.\n", __func__);

===========================================================================

However, now I am testing suspend to RAM, and I am having problems getting it working. Is there a recommended way I can force it to Gen1 that will survive a suspend/resume cycle? Note that I have applied the L2 reset patch and I am able to successfully suspend/resume using an e1000e based card. I have tried rewriting the LNK_CAP register after coming out of suspend but it does not seem to have any effect. I am thinking that I'm simply not setting it at the correct time, and hope that someone can suggest where it should go.

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1 Solution
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NXP Employee
NXP Employee

Hi:
I used to reply this customer's question by "PCIe imx6 switch issue continuation of SR 1-1159433048" , here is details.

At my side, I used the codes listed below too.

+                /* Force GEN1 */

+                writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1), dbi_base + LNK_CAP);

+               usleep_range(4000, 5000);

My tests:

Because I don’t have PLX8603 switch, I just used the i.MX6Q SD + GEN2 PCIe EP device(usb3.0 xhci device)

to do the suspend/resume tests  when the link_cap of PCIe RC(i.MX6Q SD) is limited to PCIe GEN1 speed.

Before suspend:


root@freescale ~$ lspci -vv

00:00.0 PCI bridge: Unknown device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])

...

                Device: MaxPayload 128 bytes, MaxReadReq 512 bytes

                Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 0

               Link: Latency L0s <1us, L1 <8us


After resume back:

root@freescale ~$ lspci -vv

00:00.0 PCI bridge: Unknown device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])

...

                Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch-

                Link: Speed 2.5Gb/s, Width x1

                Root: Correctable- Non-Fatal- Fatal- PME-

...


The ‘Max_Link_Speeds’ of 0x7c LNK_CAP is always 1 after out of the suspend.

root@freescale ~$ ./memtool -32 01ffc000 40

Reading 0x80 count starting at address 0x01FFC000

0x01FFC000:  ABCD16C3 00100147 06040001 00010010

0x01FFC010:  01000000 00000000 00010100 000000F0

0x01FFC020:  01100110 0000FFF0 00000000 00000000

0x01FFC030:  00000000 00000040 00000000 0001019B

0x01FFC040:  DBC35001 00000000 00000000 00000000

0x01FFC050:  01807005 00000000 00000000 00000000

0x01FFC060:  00000000 00000000 00000000 00000000

0x01FFC070:  00420010 00008000 00102010 0011CC11


Regarding to your description, it seems that the LNK_CAP is changed, right?

So I suggest customer that
"can you debug into the code, and make a check when LNK_CAP is changed?"


BTW, attached the email.



Best Regards

Richard


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2 Replies
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Senior Contributor IV

Alex, please click Correct Answer/Helpful Answer, if your question has been answered.

Thanks,

Yixing

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243 Views
NXP Employee
NXP Employee

Hi:
I used to reply this customer's question by "PCIe imx6 switch issue continuation of SR 1-1159433048" , here is details.

At my side, I used the codes listed below too.

+                /* Force GEN1 */

+                writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1), dbi_base + LNK_CAP);

+               usleep_range(4000, 5000);

My tests:

Because I don’t have PLX8603 switch, I just used the i.MX6Q SD + GEN2 PCIe EP device(usb3.0 xhci device)

to do the suspend/resume tests  when the link_cap of PCIe RC(i.MX6Q SD) is limited to PCIe GEN1 speed.

Before suspend:


root@freescale ~$ lspci -vv

00:00.0 PCI bridge: Unknown device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])

...

                Device: MaxPayload 128 bytes, MaxReadReq 512 bytes

                Link: Supported Speed 2.5Gb/s, Width x1, ASPM L0s L1, Port 0

               Link: Latency L0s <1us, L1 <8us


After resume back:

root@freescale ~$ lspci -vv

00:00.0 PCI bridge: Unknown device 16c3:abcd (rev 01) (prog-if 00 [Normal decode])

...

                Link: ASPM Disabled RCB 64 bytes CommClk- ExtSynch-

                Link: Speed 2.5Gb/s, Width x1

                Root: Correctable- Non-Fatal- Fatal- PME-

...


The ‘Max_Link_Speeds’ of 0x7c LNK_CAP is always 1 after out of the suspend.

root@freescale ~$ ./memtool -32 01ffc000 40

Reading 0x80 count starting at address 0x01FFC000

0x01FFC000:  ABCD16C3 00100147 06040001 00010010

0x01FFC010:  01000000 00000000 00010100 000000F0

0x01FFC020:  01100110 0000FFF0 00000000 00000000

0x01FFC030:  00000000 00000040 00000000 0001019B

0x01FFC040:  DBC35001 00000000 00000000 00000000

0x01FFC050:  01807005 00000000 00000000 00000000

0x01FFC060:  00000000 00000000 00000000 00000000

0x01FFC070:  00420010 00008000 00102010 0011CC11


Regarding to your description, it seems that the LNK_CAP is changed, right?

So I suggest customer that
"can you debug into the code, and make a check when LNK_CAP is changed?"


BTW, attached the email.



Best Regards

Richard


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