Hi, sorry if the question is dummy, I started to work on embedded systems some weeks ago =).
I'm working with an IMX6 Dual .
I would like to know how to set the correct value for the define "#define CONFIG_SYS_LDB_CLOCK 65000000" in the file ipu_common.c in the spl.
the settings for the display are (in both spl setup file and ldb.c kernel file):
struct fb_videomode mode_display= {
.name = "1920x720",
.refresh = 60,
.xres = 1920,
.yres = 720,
/*
LVDS-Clock:
1 / (48,7MHz * 2)
10267
*/
.pixclock = 10267,
.left_margin = 40,
.right_margin = 48,
.upper_margin = 2,
.lower_margin = 3,
.hsync_len = 40,
.vsync_len = 4,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
};
The setup_display (spl) performs the following operations (I use smooth transition since I'm displaying a splash screen):
void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU2_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
reg = readl(&mxc_ccm->CCGR3);
reg &= ~MXC_CCM_CCGR3_LDB_DI1_MASK;
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
writel(reg, &mxc_ccm->CCGR3);
#ifdef MAN_IMX_SPREAD_SPRECTRUM_ENABLED
reg = readl(&mxc_ccm->analog_pfd_528);
reg &= ~(BM_ANADIG_PFD_528_PFD2_FRAC);
reg |= BF_ANADIG_PFD_528_PFD2_FRAC(0x1C);
writel(reg, &mxc_ccm->analog_pfd_528);
/* Spread spectrum numerator */
reg =BF_ANADIG_PLL_528_DENOM_B(MAN_SPREAD_SPECTRUM_DENOM_B);
writel(reg, &mxc_ccm->analog_pll_528_denom);
reg = readl(&mxc_ccm->analog_pll_528_ss);
reg |= BF_ANADIG_PLL_528_SS_STEP(MAN_SPREAD_SPECTRUM_STEP);
reg |= BF_ANADIG_PLL_528_SS_STOP(MAN_SPREAD_SPECTRUM_STOP);
reg |= BM_ANADIG_PLL_528_SS_ENABLE; /* Enable Spread Spectrum*/
writel(reg, &mxc_ccm->analog_pll_528_ss);
reg = readl(&mxc_ccm->cs2cdr);
// Select PLL2 for ldb_diX_clk_sel
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
reg |= (MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_PLL2_396M_PFD << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cs2cdr);
#else
.... // code doesn't enter here
#endif
//Divider for 3.5
reg = readl(&mxc_ccm->cscmr2);
reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
writel(reg, &mxc_ccm->cscmr2);
//Clocks for IPU2
reg = readl(&mxc_ccm->cscdr2);
/* Use ipu2 root clock from LDB_DI0 */
reg &= ~(MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK);
reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET);
writel(reg, &mxc_ccm->cscdr2);
}
the ipu_common.c has:
#if !defined CONFIG_SYS_LDB_CLOCK
#define CONFIG_SYS_LDB_CLOCK 65000000
#endif
static struct clk ldb_clk = {
.name = "ldb_clk",
.rate = CONFIG_SYS_LDB_CLOCK,
.usecount = 0,
};
Thanks for any solution or advise.
