How to configure lpuart4 with the correct pads in the device tree for IMX93?

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How to configure lpuart4 with the correct pads in the device tree for IMX93?

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682 次查看
LAAZIBI
Contributor II

I am trying to use uart4 with flow control(cts/rts) , I tried to add the Pin Multiplexing configuration for a qs93 board like you can see below: 

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO19__LPUART4_TX		0x31e
			MX93_PAD_GPIO_IO24__LPUART4_RX		0x31e
		>;
	};

	pinctrl_uart4_rtscts: uart4-rtsctsgrp {
		fsl,pins = <
			MX93_PAD_GPIO_IO26__LPUART4_CTS_B	0x31e
			MX93_PAD_GPIO_IO18__LPUART4_RTS_B	0x31e
		>;
	};


The Pad names seems to be not correct, known that I determine them from QS93 document, the pins I wanted to use are with the same GPIOs in the pad and for sure support the LPUART4 mentioned alternative functions. 

With these configuration, my recipe build fails with:

syntax error 
FATAL ERROR: Unable to parse input tree

 How can I determine the correct pad names in this case, or where I can find the correct definition if these pads? 

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674 次查看
LAAZIBI
Contributor II

My mistake was that I determined incorrectly the pad names from the documentation, here it is the correct configuration.  

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX93_PAD_ENET2_TD0__LPUART4_TX		0x31e
			MX93_PAD_ENET2_RD0__LPUART4_RX		0x31e
		>;
	};

	pinctrl_uart4_rtscts: uart4-rtsctsgrp {
		fsl,pins = <
			MX93_PAD_ENET2_TD1__LPUART4_RTS_B	0x31e
			MX93_PAD_ENET2_RD2__LPUART4_CTS_B	0x31e
		>;
	};

 

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675 次查看
LAAZIBI
Contributor II

My mistake was that I determined incorrectly the pad names from the documentation, here it is the correct configuration.  

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX93_PAD_ENET2_TD0__LPUART4_TX		0x31e
			MX93_PAD_ENET2_RD0__LPUART4_RX		0x31e
		>;
	};

	pinctrl_uart4_rtscts: uart4-rtsctsgrp {
		fsl,pins = <
			MX93_PAD_ENET2_TD1__LPUART4_RTS_B	0x31e
			MX93_PAD_ENET2_RD2__LPUART4_CTS_B	0x31e
		>;
	};

 

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