How to boot qspi flash from GD flash(GD25q32CSIGR) on IMX6ULL board

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How to boot qspi flash from GD flash(GD25q32CSIGR) on IMX6ULL board

581 Views
allenlin
Contributor I

My board is iMX6ULL

We can use the onboard QSPI NOR flash(micron-n25q256a) to boot up RTOS

And now we need to use another QSPI NOR flash(GD25q32CSIGR) to bringup the system

Have 3 config files for 3 NOR flash under MFG tool files

qspi-nor-macronix-mx25l51245g-config
qspi-nor-micron-n25q256a-config
qspi-nor-spansion-s25fl128s-config

 

I study LUT program sequence based on macronix-mx25l51245g

Please refer as follows: 

DATA                 |   INSTR   |  PADs  |  OPERAND  | ---------------------------------------------------------------------------------- 0x08 => 000010 00    |    10     |   0    |           | >> ADDR, PAD0, 24 bit 0x18                 |           |        |   0x18    | ---------------------------------------------------------------------------------- 0x04 => 000001 00    |    1      |   0    |           | >> CMD, PAD0, 0x3B 0x0B                 |           |        |   0x0B    | ---------------------------------------------------------------------------------- 0x1C => 000111 00    |    7      |   0    |           | >> READ, PAD0, 0x04 0x04                 |           |        |   0x04    | ---------------------------------------------------------------------------------- 0x0C => 000011 00    |    3      |   0    |           | >> DUMMY, PAD0, 0x08 0x08                 |           |        |   0x08    | ---------------------------------------------------------------------------------- 0x00 => 000000 00    |    0      |   0    |           | >> STOP, PAD0, 0x00 0x00                 |           |        |   0x00    | ---------------------------------------------------------------------------------- 0x24 => 001001 00    |    9      |   0    |           | >> JMP_ON_CS, PAD0, 0x00 0x00                 |           |        |   0x00    | ----------------------------------------------------------------------------------

pastedImage_5.png

Now I trying to use LUT program sequence of macronix-mx25l51245g to boot up GD flash (GD25q32CSIGR)

Because of the GD25q32CSIGR sequence is same with macronix-mx25l51245g

Please refer as follows: 

pastedImage_6.png

But still doesn't work

Could you help me solve this problem?

Thanks !

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170 Views
igorpadykov
NXP TechSupport
NXP TechSupport

Hi Lin

most simple way to program image -  try with mfg tool, use script mfgtool2-yocto-mx-evk-qspi-nor-n25q256a.vbs

https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-6ser...

Or one can flash the qspi nor flash from tftp :

use tftp command in uboot command shell prompt:

tftp ${loadaddr} "u-boot-qspi.imx"

Then "sf probe" -> "sf erase 0x0 0x80000" ->"sf write ${loadaddr} 0x1000  0x80000"

tftp  0x90000000 "qspi-header.bin"

->"sf write 0x90000000  0x400  0x200"

Some qspi boot debugging hints are provided on

Cannot boot u-boot from QSPI on IMX7S 

Best regards
igor
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allenlin
Contributor I

Hi Igor,

Now, I am following "Getting Started with MCUXpresso SDK for i.MX 6ULL Derivatives.pdf" to programming source code on GD flash.

Chapter Five: Run a demo using Manufacturing Tool (MFGTool)

pastedImage_2.png

1. I trying to modify "mfgtool2-sdk20-mx6ul-evk-qspi-nor-n25q256a.vbs" file from 

pastedImage_3.png

to

pastedImage_4.png

and than call "mfgtool2-sdk20-mx6ul-evk-qspi-nor-n25q256a.vbs" to programming source code on the GD flash.

But doesn't work.

2. As indicated above, I also trying to modify "config" file, Please refer as follows:

0 /*dqs_loopback=0 or 1*/
0 /*hold_delay=0 to 3*/
0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
0 /*device_quad_mode_en=1 to enable sending command to SPI device*/
0 /*device_cmd=command to device for enableing Quad I/O mode*/
0 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
3 /*cs_hold_time=0 to 0xF*/
3 /*cs_setup_time=0 to 0xF*/
2000000 /*sflash_A1_size=size in byte(hex)*/
0 /*sflash_A2_size=size in byte(hex)*/
0 /*sflash_B1_size=size in byte(hex)*/
0 /*sflash_B2_size=size in byte(hex)*/
0 /*sclk_freq=0 to 6*/
0 /*busy_bit_offset=bit position of device BUSY in device status register*/
2 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
0 /*sflash_port=0 or 1 (Port B used)*/
1 /*ddr_mode_enable=0 or 1*/
0 /*dqs_enable=0 or 1*/
0 /*parallel_mode_enable=0 or 1*/
0 /*portA_cs1=0 or 1*/
0 /*portB_cs1=0 or 1*/
0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
0818040B /*lut[0] command sequence*/
1D080C08 /*lut[1] command sequence*/
0 /*lut[2] command sequence*/
0 /*lut[3] command sequence*/
0 /*lut[4] command sequence*/
0 /*lut[5] command sequence*/
0 /*lut[6] command sequence*/
0 /*lut[7] command sequence*/
0 /*lut[8] command sequence*/
0 /*lut[9] command sequence*/
0 /*lut[10] command sequence*/
0 /*lut[11] command sequence*/
0 /*lut[12] command sequence*/
0 /*lut[13] command sequence*/
0 /*lut[14] command sequence*/
0 /*lut[15] command sequence*/
0 /*lut[16] command sequence*/
0 /*lut[17] command sequence*/
0 /*lut[18] command sequence*/
0 /*lut[19] command sequence*/
0 /*lut[20] command sequence*/
0 /*lut[21] command sequence*/
0 /*lut[22] command sequence*/
0 /*lut[23] command sequence*/
0 /*lut[24] command sequence*/
0 /*lut[25] command sequence*/
0 /*lut[26] command sequence*/
0 /*lut[27] command sequence*/
0 /*lut[28] command sequence*/
0 /*lut[29] command sequence*/
0 /*lut[30] command sequence*/
0 /*lut[31] command sequence*/
0 /*lut[32] command sequence*/
0 /*lut[33] command sequence*/
0 /*lut[34] command sequence*/
0 /*lut[35] command sequence*/
0 /*lut[36] command sequence*/
0 /*lut[37] command sequence*/
0 /*lut[38] command sequence*/
0 /*lut[39] command sequence*/
0 /*lut[40] command sequence*/
0 /*lut[41] command sequence*/
0 /*lut[42] command sequence*/
0 /*lut[43] command sequence*/
0 /*lut[44] command sequence*/
0 /*lut[45] command sequence*/
0 /*lut[46] command sequence*/
0 /*lut[47] command sequence*/
0 /*lut[48] command sequence*/
0 /*lut[49] command sequence*/
0 /*lut[50] command sequence*/
0 /*lut[51] command sequence*/
0 /*lut[52] command sequence*/
0 /*lut[53] command sequence*/
0 /*lut[54] command sequence*/
0 /*lut[55] command sequence*/
0 /*lut[56] command sequence*/
0 /*lut[57] command sequence*/
0 /*lut[58] command sequence*/
0 /*lut[59] command sequence*/
0 /*lut[60] command sequence*/
0 /*lut[61] command sequence*/
0 /*lut[62] command sequence*/
0 /*lut[63] command sequence*/
1000001 /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/
0 /*enable_dqs_phase=0 or 1*/
0 /*config_cmds_en, enable config command*/
0 /*config_cmds[0]*/
0 /*config_cmds[1]*/
0 /*config_cmds[2]*/
0 /*config_cmds[3]*/
0 /*config_cmds_args[0]*/
0 /*config_cmds_args[1]*/
0 /*config_cmds_args[2]*/
0 /*config_cmds_args[3]*/
0 /*io_pad_override_setting QSPI pins override setting*/
0 /*reserve[0], 25 byte reserved area*/
0 /*reserve[1], 25 byte reserved area*/
0 /*reserve[2], 25 byte reserved area*/
0 /*reserve[3], 25 byte reserved area*/
0 /*reserve[4], 25 byte reserved area*/
0 /*reserve[5], 25 byte reserved area*/
0 /*reserve[6], 25 byte reserved area*/
0 /*reserve[7], 25 byte reserved area*/
0 /*reserve[8], 25 byte reserved area*/
0 /*reserve[9], 25 byte reserved area*/
0 /*reserve[10], 25 byte reserved area*/
0 /*reserve[11], 25 byte reserved area*/
0 /*reserve[12], 25 byte reserved area*/
0 /*reserve[13], 25 byte reserved area*/
0 /*reserve[14], 25 byte reserved area*/
0 /*reserve[15], 25 byte reserved area*/
0 /*reserve[16], 25 byte reserved area*/
0 /*reserve[17], 25 byte reserved area*/
0 /*reserve[18], 25 byte reserved area*/
0 /*reserve[19], 25 byte reserved area*/
0 /*reserve[20], 25 byte reserved area*/
0 /*reserve[21], 25 byte reserved area*/
0 /*reserve[22], 25 byte reserved area*/
0 /*reserve[23], 25 byte reserved area*/
0 /*reserve[24], 25 byte reserved area*/
c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/

 

But also doesn't work.

3. I am trying to use your suggestion, download "L4.9.88_2.0.0_mfg-tool" form NXP

and I am calling "mfgtool2-yocto-mx-evk-qspi-nor-n25q256a.vbs

but the MFGTool destruction when system power on

pastedImage_5.png

Can you description step by step, thanks.

Allen.

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