How is iMX6 PCIE endpoint MSI generation setup?

[andreaskarlsson]

Hi,

We have an iMX6S running a RTOS, the iMX6 is configured as a PCIE endpoint. Now we want to enable MSI but so far without success. There are some posts on the community but all references are using Linux and I have to agree to one post that the RM seems incomplete How to generate MSI interrupt on i.MX6 in PCIe EP/endpoint mode. From the Linux posts you can see how they conifgure PCIE_PL_MSIxx registers, I've done that in a similar fashion but no luck so far in getting MSI interrupts through to the RC. From the RM I've read following chapters, but I still can't figure out what's missing, and to be frank it is described very vague in the RM.

49.3.7.1.2 MSI

49.3.7.4 MSI Generation in the AXI Bridge

Can someone describe how it is supposed to be done when not running Linux?

Regards

Andreas

[Erans160]

I'm trying to use MSI (Message Signaled Interrupts) on an FPGA configured as a PCIe Endpoint (EP). However, I'm running into an issue where my interrupt service routine is not being triggered.

Setup Details:

• I'm check (enable) the PCIe( msi_enable ).
• I'm calling the function responsible for enabling MSI on the EP side as below:

PCIX_EnableMSI(pci_sys,bus,dev,fn,PCIE_MSI_Lisr,&MSI_Vector);

• I’ve initialized the MSI .
• During the initialization phase, the FPGA triggers the MSI by writing to a specific register (which should raise the interrupt).
• On the Root Complex (RC) side, I expect the PCIE_MSI_Lisr function to handle the interrupt.

Problem:

• The PCIE_MSI_Lisr function is never called.
• No ACK is received, so it seems like the MSI isn't going through or being handled correctly.

Questions:

1. Is there something specific I need to configure in the i.MX6 RC side to enable MSI from the EP?
2. Are there any known issues with MSI handling on this platform?

Thanks in advance for your help!

[andreaskarlsson · Accepted solution]

Finally we solved it.

1. Set and iATU if needed for outbound region to match the MSI target address assigned by the RC, can be found in 0x1FFC054

2. Do an write the local MSI address used in 1. to generate a write to the RC target address , very important to include the "RC data" in 0x1FFC05C in the MemWr. We missed this last part and did a simple write =1 as in all the Linux examples.

Regards

Andreas