How can I use ECSPI SS1-2?

[nealebuckland]

The iMX8m has ECSPI peripherals that according to the reference manual support up to four SS lines. However, in the reference manual I can only find information about how to use SS0 (e.g. via the IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 register for ECSPI1).

Where can I find information about how to use the SS1-SS2 signals?

I have found an example (DART-MX8M SPI - Variscite Wiki ) which suggests that I can use GPIO1_IO12 and GPIO1_IO15, but this doesn't seem to be documented (in the IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 and IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 registers).

[igorpadykov]

Hi neale

>Where can I find information about how to use the SS1-SS2 signals?

seems these signals are not routed externally for i.MX8M as described in

sect.8.1.1.1 Muxing Options i.MX8MDQ Reference Manual
https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf

In general in linux any gpio can be used as spi ss signal using dts property

cs-gpios : Specifies the gpio pins to be used for chipselects.

fsl-imx-cspi.txt\spi\bindings\devicetree\Documentation - linux-imx - i.MX Linux kernel 

Best regards
igor
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[nealebuckland]

So if these signals are not routed to pins, then surely all reference to the fact that the ECSPI has four slave selects should be removed from the documentation?

How does Linux manage to make use of any GPIO pin? This wiki entry: DART-MX8M SPI - Variscite Wiki 

still refers to the fact the SPI controller can support 4 slave selects:

"6 Using multiple SPI CS lines

The i.MX8M SPI controllers support up to 4 chip select lines.
In the example below GPIO1_12 and GPIO1_15 are used to control CS0 and CS1 respectively.
When selecting CS GPIO pins make sure they are not used to control other peripherals."