Hi james kim ,
Do you mean the following GPIO IRQ part:
Normally, each GPIO is divided to use 2 IRQ, one is for GPIOn 0-15, another is for 16-31.
You can understand that GPIOn 0-15 share one IRQ, GPIOn 16-31 share the other IRQ.
The detail configuration for the shared GPIO IRQ can be found in the RM Chapter 12
General Purpose Input/Output (GPIO), you can find related register, ICR, IMR, ISR. etc.
The SDK sample code is used this combined mode.
But GPIO1 is special, it is related to the INT0-7, you can refer to this post:
https://community.nxp.com/thread/303144
My understanding is the INT0-INT7 is related to the GPIO1_0 to GPIO1_7, then the active HIGH interrupt, you can try to configure ICR1_ICR0 to ICR1_ICR7 to 01b - Interrupt n is high-level sensitive, then enable the related IRQ, and check whether it works or not.
You can try it on your side.
If you still have question about it, please kindly let me know.
Kerry
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Thanks for the info Kerry.
I followed the NXP GPIO input example but I am getting
Debug trace shows me that there is an issue with IRQ Handler:
Exactly following the example, I added the following in my code:
Honestly this is really a magic to me and I don't understand how this #define works.
#define GPIO1_Combo_0_15_IRQHandler GPIO1_Combined_0_15_IRQHandler
void GPIO1_Combo_0_15_IRQHandler(void)
{
uint32_t interrupt_status = GPIO_PortGetInterruptFlags(gpio5);
// Check for registered interrupt callback
for (uint32_t i = 0; i < sizeof(interrupt_status); i++)
{
if (interrupt_status & 1U << i)
{
// Invoke registered callback
// Clear the interrupt status
GPIO_PortClearInterruptFlags(gpio5, 1U << i);
}
}
}
Interrupt fault occurs right at the end of the following code:
EnableIRQ(GPIO1_Combined_0_15_IRQn);
gpio_config.direction = kGPIO_DigitalInput;
gpio_config.interruptMode = kGPIO_IntLowLevel;
GPIO_PinInit(GPIO1, 3, &gpio_config);
GPIO_PortEnableInterrupts(GPIO1, 1U << 3);
Could you help me?
Hi james kim,
Which detail pin you want to as the GPIO interrupt? IOMUXC_GPIO_AD_B0_03_GPIO1_IO03, this one?
If yes, do you configure this pin as the GPIO function in the pin_mux.c?
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_03_GPIO1_IO03,
0U);
The GPIO interrupt configure code should be:
gpio_pin_config_t sw_config = {
kGPIO_DigitalInput,
0,
kGPIO_IntRisingEdge,
};
EnableIRQ(GPIO1_Combined_0_15_IRQn);
GPIO_PinInit(GPIO1, 3U, &sw_config);
/* Enable GPIO pin interrupt */
GPIO_PortEnableInterrupts(GPIO1, 1U << 3);
#define EXAMPLE_GPIO_IRQHandler GPIO1_Combined_0_15_IRQHandler
void EXAMPLE_GPIO_IRQHandler(void)
{
/* clear the interrupt status */
GPIO_PortClearInterruptFlags(GPIO1, 1U << 3);
/* Change state of switch. */
g_InputSignal = true;
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
Then you can write the interrupt handler code in the EXAMPLE_GPIO_IRQHandler , EXAMPLE_GPIO_IRQHandler = GPIO1_Combined_0_15_IRQHandler, just redefine the interrupt handler name.
I suggest you test the SDK GPIO interrupt sample code directly at first, after it works, then you can modify the GPIO pin to your own pin.
If you still have issues about it, please kindly let me know.
Wish it helps you!
Kerry
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Hi james kim,
Thanks for your updated information.
Tody, I test the GPIO1_3 highlevel interrupt, it works OK, and the interrupt can be cleaned.
So, your issue should still in the code side.
Please check my attached project which is based on the C code.
I have tested it, it works OK.
When your GPIO_AD_B0_03_GPIO1_IO0 input high level, the interrupt will be triggered, then you input GPIO_AD_B0_03_GPIO1_IO0 as low, the printf will give the related log
You also can check my project, if you are using the MIMXRT1050-EVKB board, the GPIO pin is J24-1.
Wish it helps you!
If you still have question about it, please kindly let me know.
Kerry
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