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Interrupts with GPIO1 INT0-7

Question asked by Ben Anderson on Jan 7, 2013
Latest reply on Oct 8, 2019 by Michael Richmond

I am then stuck with needing a gpio that I can use as an interrupt that can also have its cpu affinity changed.  From the freescale imx6 documentation it list several gpio interrupts within the 255 limit.   See this previous post for info on why I want a interrupt below 255:


*** In the below I am referencing Rev. 0, 11/2012 of the  i.MX 6Dual/6Quad Applications Processor Reference Manual.


I can not find any indication in either the interrupt or the GPIO chapter how the GPIO1 is configured to deliver these interrupts.


Here is a table for the reference manual that shows the IRQ number and source.  However it lists the source as just GPIO1.  I am not sure what GPIO in GPIO1 maps to which INT0-7.  For example does GPIO1_1 map to INT1?   It is also possible I just don't understand how the gpio's work with the interrupts in general.  There seems very little information about this subject in the documentation.



Table 3-1.



90 GPIO1 INT7 interrupt request.

91 GPIO1 INT6 interrupt request.

92 GPIO1 INT5 interrupt request.

93 GPIO1 INT4 interrupt request.

94 GPIO1 INT3 interrupt request.

95 GPIO1 INT2 interrupt request.

96 GPIO1 INT1 interrupt request.

97 GPIO1 INT0 interrupt request.





I also see that in mx6.h I have the following.  Which matches up with documentation.


#define MXC_INT_GPIO1_INT7_NUM90
#define MXC_INT_GPIO1_INT6_NUM91
#define MXC_INT_GPIO1_INT5_NUM92
#define MXC_INT_GPIO1_INT4_NUM93
#define MXC_INT_GPIO1_INT3_NUM94
#define MXC_INT_GPIO1_INT2_NUM95
#define MXC_INT_GPIO1_INT1_NUM96
#define MXC_INT_GPIO1_INT0_NUM97
#define MXC_INT_GPIO1_INT15_0_NUM98
#define MXC_INT_GPIO1_INT31_16_NUM99
#define MXC_INT_GPIO2_INT15_0_NUM100
#define MXC_INT_GPIO2_INT31_16_NUM101
#define MXC_INT_GPIO3_INT15_0_NUM102
#define MXC_INT_GPIO3_INT31_16_NUM103
#define MXC_INT_GPIO4_INT15_0_NUM104
#define MXC_INT_GPIO4_INT31_16_NUM105
#define MXC_INT_GPIO5_INT15_0_NUM106
#define MXC_INT_GPIO5_INT31_16_NUM107
#define MXC_INT_GPIO6_INT15_0_NUM108
#define MXC_INT_GPIO6_INT31_16_NUM109
#define MXC_INT_GPIO7_INT15_0_NUM110
#define MXC_INT_GPIO7_INT31_16_NUM111





The manual also has this tidbit about how the GPIO's and Interrupts work.  However I not sure I gain any more insight.




28.2 General Overview



Each GPIO input has a dedicated edge-detect circuit which can be configured through

software to detect rising edges, falling edges, logic low-levels or logic high-levels on the

input signals. The outputs of the edge detect circuits are optionally masked by setting the

corresponding bit in the interrupt mask register (GPIO_IMR). These qualified outputs are

OR'ed together to generate two one-bit interrupt lines:


• Combined interrupt indication for GPIOx signals 0 - 15

• Combined interrupt indication for GPIOx signals 16 - 31


In addition, GPIO1 provides visibility to each of its 8 low order interrupt sources (i.e.

GPIO1 interrupt n, for n = 0 – 7). However, individual interrupt indications from other

GPIOx are not available.



The last paragraph is the most helpful (in bold) but it doesn't seem to say anything different then table 3-1 except that it kinda seems to indicate a 0-0, 1-1 mapping but not sure.


I have a driver with a "normal" interrupt working already.  The problem is that these interrupts are registered outside of the irq 255 limit for moving to different cores.


I have a driver registering irq 92 (GPIO1 INT5) but the system does not ever raise this interrupt when I trigger GPIO1_5.  I also tried registering both irq 92 and the "normal" GPIO1_5 interrupt (irq number 292) with the same result.



Is there somewhere I can get more information or does someone have examples on how to use these gpio irqs?





Ben Anderson


i.mx6 Linux CPU IRQ affinity