Frame buffer update in IMX MIPI DSI driver (i.MX8MQ)

[devendradevadig]

Dear Team,
I am working i.MX8MQ platform with Linux 5.4.70.
I want to understand, inside the driver how to update MIPI DSI frame buffer.

I traced the LCDIF driver and I came to know that, for updating the frame buffer we need to write the address of frame buffer in LCDC_V4_NEXT_BUF (0x50) register.

Something like this :
write(addrees_of_frame_buffer, lcd_base + LCDC_V4_NEXT_BUF )

#define LCDC_V4_NEXT_BUF 0x50

.next_buf = LCDC_V4_NEXT_BUF,

writel(fb_info->fix.smem_start +
fb_info->fix.line_length * fb_info->var.yoffset,
host->base + host->devdata->next_buf);

So every time when we write to /dev/fb0, above line will execute inside the driver in case of LCDIF driver.

Similarly for MIPI DSI, inside the driver where this frame buffer update will happen when we write to /dev/fb0 ?
Which line will execute inside the driver for updating the frame buffer ?
For what register we need to update frame buffer address? Please can you help me on this?

I tried to put the prints in driver. Whenever I write to /dev/fb0, I am getting prints like below:

root@imx8m-iwg33m:~#
root@imx8m-iwg33m:~# cat slide2 > /dev/fb0
[ 1486.704540]
[ 1486.704540] drm_fb_helper_sys_write
[ 1486.709810]
[ 1486.709810] drm_fb_helper_sys_write
[ 1486.715032]
[ 1486.715032] drm_fb_helper_sys_write
.........
root@imx8m-iwg33m:~#

In weston graphics case, I am getting like below:

root@imx8m-iwg33m:~# weston-start
root@imx8m-iwg33m:~# [ 1490.505543]
[ 1490.505543] dcss-plane.c: dcss_plane_atomic_update -> dcss_scaler_setup

root@imx8m-iwg33m:~#
root@imx8m-iwg33m:~#
root@imx8m-iwg33m:~# killall weston
root@imx8m-iwg33m:~# [ 1697.444226]
[ 1697.444226] dcss-plane.c: dcss_plane_atomic_update -> dcss_scaler_setup

root@imx8m-iwg33m:~#

In file drivers/gpu/drm/drm_fb_helper.c (drm_fb_helper_sys_write->fb_sys_write) frame buffer will be copied. But in MIPI DSI (DRM) side where this frame buffer update is happening ?
Please can you refer me source file and line number ?

Thanks and Regards,
Devendra

[devendradevadig · Accepted solution]

Dear Sir,

Thanks for your support.

I worked on LCDIF driver. You can close this.

Thanks and Regards,

Devendra

[igorpadykov]

Hi Devendra

frame buffer support for i.MX8 in nxp bsps is described in   i.MX Linux Reference Manual​   below

 

Best regards
igor

[devendradevadi1]

Dear Sir,

Thanks for the information. 

But whenever I dump the data to /dev/fb0 it is displayed on the screen. So think below driver will be used, which will once again may use DCSS driver in linux:

drivers/gpu/drm/drm_fb_helper.c -> drivers/video/fbdev/core/fb_sys_fops.c

Currently I am not looking for a this existing frame buffer driver.

We are using DCSS controller and MIPI DSI interface. 

Actually, what I am looking is like, inside the DCSS or MIPI DSI driver where frame buffer is updating as I mentioned in previous comment for LCDIF controller case.

I tried to refer U-Boot and Linux source code and came to know that if we use DCSS controller, the physical address of frame buffer need to be update in below registers:

Frame 1-Plane Base Address Control 0 (FRAME_1P_BASE_ADDR_CTRL0) 

Frame 2-Plane Base Address Control 0 (FRAME_2P_BASE_ADDR_CTRL0)

Above information I got by refering U-Boot 2018 source code :

arch/arm/mach-imx/imx8m/video_common.c -> imx8m_display_init()

/* CHAN1_DPR */
reg32_write(REG_BASE_ADDR + 0x180c0, (unsigned int)buffer);

reg32_write(REG_BASE_ADDR + 0x18110,
(unsigned int)buffer + vms->xres * vms->yres);

As in LCDIF controller case, just updating the frame buffer physical address is enough? or Do we need to set or clear any bit in any of register, after data comes in frame buffer ?

In datasheet, there is a section like "DPR Memory map",

15.7.3.1.2 System Control 0 (SYSTEM_CTRL0) its mentioned like for next frame "Shadow Load Enable" bit need to set. similarly RUN_EN need to set.

In "Scale Control Register (SCALE_CTRL)" register it mentioned like we need to set "ENABLE_SCALR" bit.

Assume I have own FB driver and configured the shared memory for writing frame buffer data. 

If I have custom DCSS driver will all basic setup/register initalization done (by Refering U-boot code as above mentioned -> imx8m_display_init()), whenevr I write the data to /dev/fb, for updating DCSS side what operation I need to do ?

Is above steps enough ? i.e

1. Update frame buffer address to FRAME_1P_BASE_ADDR_CTRL0 and FRAME_2P_BASE_ADDR_CTRL0

2. In register SYSTEM_CTRL0, set the bits SHADOW_LOAD_EN and RUN_EN

3. In register SCALE_CTRL, set ENABLE_SCALR bit

Thank you in advance. Waiting for any ones reply/help.

Regards,

Devendra

[igorpadykov]

Hi Devendra

one can look at ../drivers/gpu/drm/bridge/nwl-dsi

https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/nwl-dsi/nwl-drv.c?h...

Sources are described in Table 65. MIPI DSI Driver Files  i.MX Linux Reference Manual​

Best regards
igor