First time power on sequence of i.MX7D-SABRE

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First time power on sequence of i.MX7D-SABRE

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takayuki_ishii
Contributor V

Hello community,

In i.MX7D-SABRE, if 5VDC in and SW1 on, board will start up immediately.

We hope to keep OFF mode after SW1 on  and start boot up by pushed ONOFF button.

In Table 6-8. Power mode transitions of i.MX7 reference manual (IMX7DRM rev1),

It say that  "2. When button is pressed, 'state' goes ON,PMIC_ON_REQ goes '1'."

Does we can control by ONOFF button of first time power on sequence?

I already removed both R280 and R307 registers connect to PWRON pin of PMIC.

Best regards,

Ishii.

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Yuri
NXP Employee
NXP Employee

Hello,

 

 

  After VDD_SNVS_IN is ON, PMIC_ON_REQ is asserted, therefore hardly

it is possible to avoid system start at the first time power on.

 

  Also, please take in account the following: it is highly recommended

to remove power (voltage source) to all components on the board in

the event of a processor reset. This avoids having to determine if a component

critical to rebooting the processor is in the necessary state to support

a reboot. Such devices as eMMC memory card (if the hardware RST_B pin

is not connected), SD Card (if the reset pin is not used to remove power to the

SD Card), QSPI, NOR, LPDDR2/3 memory may be left in improper state after

CPU reset.

 

 

Have a great day,

Yuri

 

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1,291 次查看
Yuri
NXP Employee
NXP Employee

Hello,

 

 

  After VDD_SNVS_IN is ON, PMIC_ON_REQ is asserted, therefore hardly

it is possible to avoid system start at the first time power on.

 

  Also, please take in account the following: it is highly recommended

to remove power (voltage source) to all components on the board in

the event of a processor reset. This avoids having to determine if a component

critical to rebooting the processor is in the necessary state to support

a reboot. Such devices as eMMC memory card (if the hardware RST_B pin

is not connected), SD Card (if the reset pin is not used to remove power to the

SD Card), QSPI, NOR, LPDDR2/3 memory may be left in improper state after

CPU reset.

 

 

Have a great day,

Yuri

 

------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer

button. Thank you

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takayuki_ishii
Contributor V

Hello Yuri,

Thank you for your response.

I will answer it to my customer.

Best regards,

Ishii.

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