Fec rmii imx93

[jsangwan]

&fec {

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_fec>;

phy-mode = "rmii";

phy-handle = <&ethphy2>;

fsl,magic-packet;

fsl,rmii_refclk_ext; // PHY provides 50MHz reference clock

enet_clk_sel = <&wakeupmix_gpr 0x2C>; // Required for RMII clock selection

status = "okay";

// PHY reset configuration

phy-reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;

phy-reset-duration = <10>;

phy-reset-post-delay = <10>;

mdio {

#address-cells = <1>;

#size-cells = <0>;

clock-frequency = <5000000>;

ethphy2: ethernet-phy@0 {

compatible = "ethernet-phy-ieee802.3-c22";

reg = <0>;

reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;

reset-assert-us = <10000>;

reset-deassert-us = <30000>;

max-speed = <100>; // RMII supports up to 100Mbps

};

};

};

these are my dts configrations i have a phy that generates clock 

in this configration eth0 pops up but only tx packets come up in ifconfig no rx packet 

pinctrl_fec: fecgrp {

fsl,pins = <

// MDIO interface

MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e

MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e

// RMII data pins

MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e

MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e

MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e

MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e

MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e

MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e

MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000057e

// PHY reset pin

MX93_PAD_GPIO_IO25__GPIO2_IO25 0x3fe

>;

};

[Zhiming_Liu]

Hi,

Please measure the TX_CLK pin with an oscilloscope to see if there is really a 50MHz square wave.

Your configuration is as follows:

//
phy-reset-duration = <10>;
phy-reset-post-delay = <10>;

//
reset-assert-us = <10000>;
reset-deassert-us = <30000>;

This is redundant, usually just the reset-gpios inside the mdio will suffice, it is recommended to keep only one reset control.

Best Regards,
Zhiming