Request for Linker Script to Place Code/Data in TCM (Cortex-M7, i.MX8MP)

[adithya369]

I am currently working on the Cortex-M7 core of the i.MX8MP platform and am trying to place all the code and data sections into TCM  (ITCM and DTCM) to ensure optimal performance. However, I have not been successful in modifying the linker script accordingly, as the existing memory configuration and placement logic are a bit unclear to me.

Could you kindly provide a working linker script or an example configuration that correctly places all code and data segments into the TCM regions for the Cortex-M7 on this platform?

This would greatly help me proceed with development and ensure the application runs from the fastest available memory.

Thank you in advance for your support.

[Zhiming_Liu]

Hi,

Please refer the linker file in sdk exmaple: https://github.com/nxp-mcuxpresso/mcux-sdk-examples/blob/MCUX_2.16.100/evkmimx8mp/multicore_examples...

Best Regards,
Zhiming

[adithya369]

Hi Ziming,
Thanks for the response.
I'm working on the Cortex-M7 core of the i.MX8M Plus and evaluating GPIO toggling performance using direct register access.

Currently, I'm observing a GPIO toggling time of ~250ns per edge (~2MHz frequency).

How can we achieve better performance?

Best Regards,
adithya

[Zhiming_Liu]

Hi @adithya369 

Please use below setting about pad configuration.

The test code should like this:

Best Regards,
Zhiming

[adithya369]

Hi,
From your advise to explicitly set the slew rate for pad configuration using the following macro:
#define GPIO_CONFIG ( \
IOMUXC_SW_PAD_CTL_PAD_PE(1U) | /* Pull Enable */ \
IOMUXC_SW_PAD_CTL_PAD_PUE(1U) | /* Pull Up */ \
IOMUXC_SW_PAD_CTL_PAD_DSE(3U) | /* Drive Strength = medium */ \
IOMUXC_SW_PAD_CTL_PAD_FSEL(1U)| /* Function select = 1 */ \
IOMUXC_SW_PAD_CTL_PAD_SRE(1U) /* Fast slew rate */ \
)
However, after adding the IOMUXC_SW_PAD_CTL_PAD_SRE(1U) line, I get the following build error:
error: implicit declaration of function 'IOMUXC_SW_PAD_CTL_PAD_SRE'; did you mean 'IOMUXC_SW_PAD_CTL_PAD_ODE'? [-Wimplicit-function-declaration]
My Questions:

Is IOMUXC_SW_PAD_CTL_PAD_SRE missing or not defined in this SDK?

What is the correct way to set slew rate for a GPIO pin on this platform?

Could this be a header file or SoC support issue?

I followed the recommended approach, but now I’m stuck due to this build failure. Any help or clarification would be appreciated.

Thanks and regards,
Adithya.

[Zhiming_Liu]

Hi,

Please use IOMUXC_SW_PAD_CTL_PAD_FSEL

#define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK          (0x18U)
#define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT         (3U)
/*! FSEL - Slew Rate Field
 *  0b0x..Select slow slew rate (SR=1)
 *  0b1x..Select fast slew rate (SR=0)
 */
#define IOMUXC_SW_PAD_CTL_PAD_FSEL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK)

Best Regards,
Zhiming

[adithya369]

Hi @Zhiming,
Thanks for the response.
#define GPIO_CONFIG ( \
IOMUXC_SW_PAD_CTL_PAD_DSE(6U) | \
IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | \
IOMUXC_SW_PAD_CTL_PAD_PE_MASK | \
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | \
IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK)

added this config
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD1_GPIO4_IO03, GPIO_CONFIG); // add0
but still the toggling speed is not changed

[adithya369]

Hi @zhiming,
Any update on this???