Enabling SPI Slave Device under /dev on i.MX93QSB

[sergiomauro]

Hello NXP Community,

I am working on an SPI communication project using the i.MX93QSB and Linux kernel 6.1.

My goal is to set up both SPI master and SPI slave on the same board to test data exchange. I’ve followed the NXP examples for configuring SPI in both master and slave modes in the device tree, and I’ve encountered some challenges with accessing the SPI slave in user space.

What I've Done So Far

• SPI Master Configuration: I used the example in imx93-9x9-qsb-lpspi.dts (linux-imx/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi.dts at lf-6.1.y · nxp-imx/linux-imx · Gi...) to configure lpspi3 in master mode. With this setup, I can see "/dev/spidevX.Y" and successfully test loopback by connecting MISO and MOSI.
  
  
• SPI Slave Configuration: For slave mode, I followed the example in imx93-9x9-qsb-lpspi-slave.dts (linux-imx/arch/arm64/boot/dts/freescale/imx93-9x9-qsb-lpspi-slave.dts at lf-6.1.y · nxp-imx/linux-imx...) in which it is used the "spi-slave" keyword. However, in this configuration, there’s no device under "/dev" for the SPI slave. Instead, I only see the slave node under "/sys/class/spi_slave/spiX".

Objective

I would like to set up both SPI master and SPI slave on the i.MX93QSB and interact with both in user space. Ideally, I want an interface for the SPI slave under "/dev" (similar to spidev) so I can open both devices in a single C program for master-slave communication testing on the same board.

I tried to remove the "/delete-node/ spi@0;" line from the slave device tree but received the following error:

After all this, what I ask is if it possible to enable a "/dev" interface for an SPI slave on the i.MX93QSB? If so, what modifications would be needed in the device tree?

Any guidance on creating a "/dev" interface for the SPI slave on i.MX93QSB, or tips from others who’ve encountered similar challenges, would be greatly appreciated!

Thank you for your help!
Sergio

[Chavira · Accepted solution]

HI @sergiomauro!

Thank you for contacting NXP Support!

I used the LPSPI8 as a slave in iMX93 QSB and that are the steps that I followed :

Tested on BSP 6.1.55

1) I modify the original Device tree and the final result is the next:

The LPSPI3 is Master and LPSPI8 is Slave

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2022 NXP
 */

#include "imx93-9x9-qsb.dts"

&sai3 {
	status = "disabled";
};

/*
LPSPI3 Master Mode

PAD_NAME    FUNCTION        QSB J1401

GPIO_IO08   CS              24   
GPIO_IO09   LPSPI3_SIN      21
GPIO_IO10   LPSPI3_SOUT     19
GPIO_IO11   LPSPI3_SCK      23

*/

&lpspi3 {
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpspi3>;
	pinctrl-1 = <&pinctrl_lpspi3>;
	cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
	/*
	 * Switch the SPI pins to RPi connector for testing.
	 * It will also control the pins of SAI3, so SAI3 is disabled above.
	 */
	pinctrl-assert-gpios = <&pcal6524 22 GPIO_ACTIVE_HIGH>;
	status = "okay";

	spidev0: spi@0 {
		reg = <0>;
		compatible = "lwn,bk4";
		spi-max-frequency = <1000000>;
	};
};


/*
LPSPI8 Slave Mode

PAD_NAME    FUNCTION        QSB J1401

GPIO_IO12   CS              32   
GPIO_IO13   LPSPI8_SIN      35
GPIO_IO14   LPSPI8_SOUT     8
GPIO_IO15   LPSPI8_SCK      10

*/

&lpspi8{
	#address-cells = <0>;
	fsl,spi-num-chipselects = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_lpspi8>;
	pinctrl-1 = <&pinctrl_lpspi8>;
	
	spi-slave;
	status = "okay";
};

&iomuxc {

	pinctrl_lpspi8: lpspi8grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO12__LPSPI8_PCS0		0x3fe
			MX93_PAD_GPIO_IO13__LPSPI8_SIN		0x3fe
			MX93_PAD_GPIO_IO14__LPSPI8_SOUT		0x3fe
			MX93_PAD_GPIO_IO15__LPSPI8_SCK		0x3fe
		>;
	};

	pinctrl_lpspi3: lpspi3grp {
		fsl,pins = <
			MX93_PAD_GPIO_IO08__GPIO2_IO08		0x3fe
			MX93_PAD_GPIO_IO09__LPSPI3_SIN		0x3fe
			MX93_PAD_GPIO_IO10__LPSPI3_SOUT		0x3fe
			MX93_PAD_GPIO_IO11__LPSPI3_SCK		0x3fe
		>;
	};
};

2) Connect the LPSPI8 to LPSPI3 using wires, the connection is the next:

LPSPI3 Master Mode

PAD_NAME    FUNCTION        QSB J1401

GPIO_IO08   CS              24  

GPIO_IO09   LPSPI3_SIN      21

GPIO_IO10   LPSPI3_SOUT     19

GPIO_IO11   LPSPI3_SCK      23

LPSPI8 Slave Mode

PAD_NAME    FUNCTION        QSB J1401

GPIO_IO12   CS              32  

GPIO_IO13   LPSPI8_SIN      33

GPIO_IO14   LPSPI8_SOUT     8

GPIO_IO15   LPSPI8_SCK      10

                                   RPI HEADER

    MASTER                      --->              SLAVE

FUNCTION          PIN      --->     FUNCTION          PIN

     CS                  24       --->          CS                   32

     SIN                  21       --->          SIN                  33

     SOUT               19       --->          SOUT              08            

     SCK                 23       --->         SCK                 10

2) Load the device tree to the board and use the next commands:

$ echo bk4 > /sys/class/spi_slave/spi0/slave
$ spidev_test -D /dev/spidev0.0 -p slave-hello-to-master &
$ spidev_test -D /dev/spidev1.0 -v -p master-hello-to-slave

After the first command the slave should appear in "/dev"

EXPECTED RESULT IN LINUX TERMINAL

root@imx93evk:~# echo bk4 > /sys/class/spi_slave/spi0/slave
root@imx93evk:~# spidev_test -D /dev/spidev0.0 -p slave-hello-to-master &
[1] 495
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 kHz)
root@imx93evk:~# spidev_test -D /dev/spidev1.0 -v -p master-hello-to-slave
spi mode: 0x0
bits per word: 8
max speed: 500000 Hz (500 kHz)
TX | 6D 61 73 74 65 72 2D 68 65 6C 6C 6F 2D 74 6F 2D 73 6C 61 76 65 __ __ __ __ __ __ __ __ __ __ __  |master-hello-to-slave|
RX | 73 6C 61 76 65 2D 68 65 6C 6C 6F 2D 74 6F 2D 6D 61 73 74 65 72 __ __ __ __ __ __ __ __ __ __ __  |slave-hello-to-master|
[1]+  Done                    spidev_test -D /dev/spidev0.0 -p slave-hello-to-master
root@imx93evk:~#

I attached the patch that I made for this case.

Best Regards!

Chavira

[lluo]

Hi @Chavira ，

I have some questions regarding the wire connections in the example you provided. In the example, the sout of the master connects to the sout of the slave while the sin of the master connects to the sin of the slave.  Why is it like this? 

From my understanding , the sout of the spi master should connect to the sin of the spi slave, and the sin of the spi master should connect to the sout of the spi slave.  Do you probably explain a bit more about the spi wire connection provided in your example? I am looking forward to your early reply. Thank you in advance.

[sergiomauro]

Hello,

Thank you for your response-definitely one of the best I've received! The patch was extremely helpful and succesfully fixed the spidev slave issue under the /dev directory in Linux. After applying it, the next test run with the SPI communication worked perfectly.

One small note: I noticed in your screenshot, the root is labeled "iMX93EVK". In my case, I cross-compiled the Linux imx93-9x9-lpddr4-qsb 6.1.55 sources for the "iMX93QSB": everything worked smoothly.

Thanks again!