Simple SDI to CSI bridge to i.mx8mp

[nickt1]

We have a custom board, running Debian Bookworm, which uses an FPGA to bridge SDI video to CSI2. The FPGA i2c interface is quite simple as the SDI signal controls the video format, which is either 720p or 1080p at various frame rates. All frame rates use a CSI clock of 300MHz and a data rate of 600MHz over 4 lanes.

I have written a sub-device driver which (I think) uses the CSI2-SAM. With a 720p 50Hz input I see:

$ media-ctl -d /dev/media0 -p                                                   Media controller API version 6.1.36

Media device information
------------------------
driver          mxc-md
model           FSL Capture Media Device
serial
bus info        platform:32c00000.bus:camera
hw revision     0x0
driver version  6.1.36

Device topology
- entity 1: mxc_isi.0 (16 pads, 2 links)
            type V4L2 subdev subtype Unknown flags 0
        pad0: Sink
                <- "mxc-mipi-csi2.0":4 [ENABLED]
        pad1: Sink
        pad2: Sink
        pad3: Sink
        pad4: Sink
        pad5: Sink
        pad6: Sink
        pad7: Sink
        pad8: Sink
        pad9: Sink
        pad10: Sink
        pad11: Sink
        pad12: Source
                -> "mxc_isi.0.capture":0 [ENABLED]
        pad13: Source
        pad14: Source
        pad15: Sink

- entity 18: mxc_isi.0.capture (1 pad, 1 link)
             type Node subtype V4L flags 0
             device node name /dev/video3
        pad0: Sink
                <- "mxc_isi.0":12 [ENABLED]

- entity 22: mxc-mipi-csi2.0 (8 pads, 2 links)
             type Node subtype V4L flags 0
             device node name /dev/v4l-subdev0
        pad0: Sink
                <- "mc_camera_mipi 3-003c":0 [ENABLED,IMMUTABLE]
        pad1: Sink
        pad2: Sink
        pad3: Sink
        pad4: Source
                -> "mxc_isi.0":0 [ENABLED]
        pad5: Source
        pad6: Source
        pad7: Source

- entity 31: mc_camera_mipi 3-003c (1 pad, 1 link)
             type V4L2 subdev subtype Sensor flags 0
             device node name /dev/v4l-subdev1
        pad0: Source
                [fmt:UYVY8_2X8/1280x720 field:none colorspace:rec709 xfer:709 ycbcr:601 quantization:lim-range]
                -> "mxc-mipi-csi2.0":0 [ENABLED,IMMUTABLE]

This seem about right to me.

Initially I notice:

/sys/devices/platform/soc@0/32c00000.bus/32c00000.bus:camera/32e40000.csi$ cat ./power/runtime_status
suspended

That's fine as I have not started a capture.

Then I run:

$ v4l2-ctl --set-fmt-video=width=1280,height=720,pixelformat="NV12" --device=/dev/video3 --stream-count=10 --stream-mmap

and the runtime status changes to 'active'. Using a 'scope I notice that the FPGA starts outputting CSI video data as requested by the sub-device as it gets:

[326921.869991] mc_camera_mipi 3-003c: s_stream: 1

get_fmt returns a code of 0x2006 (MEDIA_BUFS_FMT_UYVY8_2x8) which matches the documented output format of UYVY8. It also outputs the resolution and frame rate detected by the FPGA.

This all looks fine to me, but the v4l2 capture stalls waiting for the first frame:

ioctl(3, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, fmt.pix_mp={width=1280, height=720, pixelformat=v4l2_fourcc('N', 'V', '1', '2') /* V4L2_PIX_FMT_NV12 */, field=V4L2_FIELD_NONE, colorspace=V4L2_COLORSPACE_SRGB, plane_fmt=[{sizeimage=1382400, bytesperline=1280}], num_planes=1}}) = 0
ioctl(3, VIDIOC_STREAMON, [V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE]) = 0
ioctl(3, VIDIOC_G_FMT, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, fmt.pix_mp={width=1280, height=720, pixelformat=v4l2_fourcc('N', 'V', '1', '2') /* V4L2_PIX_FMT_NV12 */, field=V4L2_FIELD_NONE, colorspace=V4L2_COLORSPACE_SRGB, plane_fmt=[{sizeimage=1382400, bytesperline=1280}], num_planes=1}}) = 0
pselect6(4, NULL, NULL, [3], {tv_sec=0, tv_nsec=0}, NULL) = 0 (Timeout)
ioctl(3, VIDIOC_DQBUF, {type=V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE

So obviously something is wrong here.

I'm a bit of a noob with V4L2, though I have written a driver for a PCIe based video capture, with similar PCIe interface.

Any suggestion as to what tools I can apply to debugging this, or hint as to what I have wrong would be gratefully received,

Thanks

P.S. snippets from the device tree follow

&i2c4 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c4>;
	pinctrl-1 = <&pinctrl_i2c4_gpio>;
	scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	status = "okay";

	mc_camera_mipi0 {
		compatible = "v4,mc_camera_mipi";
		reg = <0x3c>;
		clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		clock-names = "xclk";
/* Disabled CLKO2, since DART-MX8MP camera expansion board uses
 * its own oscillator. Enable CLK02 if your desing requres it
 */
#if 0
		assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
#endif
		assigned-clock-rates = <24000000>;
		csi_id = <0>;
/*		powerdown-gpios = <&pca6408_1 2 GPIO_ACTIVE_HIGH>;
		reset-gpios = <&pca6408_1 0 GPIO_ACTIVE_LOW>;
*/
		mclk = <24000000>;
		mclk_source = <0>;
		mipi_csi;
		status = "okay";

		port {
			mc_camera_mipi_0_ep: endpoint {
				remote-endpoint = <&mipi_csi0_ep>;
				data-lanes = <1 2 3 4>;
				clock-lanes = <0>;
			};
		};
	};
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&mc_camera_mipi_0_ep>;
			data-lanes = <4>;
			csis-hs-settle = <6>;
			csis-clk-settle = <2>;
			csis-wclk;
		};
	};
};

    mipi_csi_0: csi@32e40000 {
     compatible = "fsl,imx8mp-mipi-csi", "fsl,imx8mn-mipi-csi";
     reg = <0x32e40000 0x10000>;
     interrupts = <0 17 4>;
     clock-frequency = <500000000>;
     clocks = <&clk 271>,
       <&clk 97>,
       <&clk 269>;
     clock-names = "mipi_clk",
            "disp_axi",
            "disp_apb";
     assigned-clocks = <&clk 170>;
     assigned-clock-parents = <&clk 65>;
     assigned-clock-rates = <500000000>;
     bus-width = <4>;
     csi-gpr = <&mediamix_gasket0>;
     gpr = <&media_blk_ctrl>;
     power-domains = <&media_blk_ctrl 1>;
     status = "disabled";
    };

[nickt1 · Accepted solution]

CSI timing issues

[doomankim]

Hi ,  I'm struggling with HD-SDI to MIPICIS2 bridge solution on linux based platform. 

Could you recommend me your chipset solution?