DDR3 datastrobe length matching

[mylsamy_m]

Hi,

I am using iMX6 Dual lite processor, In which DDR3 we are doing the layout 4 DDR3 chips with Fly-by topology.

We are doing the Address,cmd and ctrl lines length matching tightly with clock pair and data byte with data mask and strobe tight length matching. Do we need to length match Data strobe also with respect to clock pair? because i noticed we have write and read leveling in DDR3 

so,planning to adjust the write\read leveling instead of matching data strobe with respect to clock of each chip. is that works? also these write \read level adjustment should be done iMx6 or DDR chips?

Thanks and Regards

[mylsamy_m]

Hi, 

 i want to know the IMX6 dual lite DDR3 read write delay value. can you please help on that.

Thanks and Regards,

[igorpadykov]

for details please refer to AN4467 i.MX 6 Series DDR Calibration

https://www.nxp.com/docs/en/application-note/AN4467.pdf 

Best regards
igor

[igorpadykov]

Hi Mylsamy

>Do we need to length match Data strobe also with respect to clock pair?

yes as described in i.MX6 System Development User’s Guide, though

there is have write and read leveling, their ability may be not sufficient to

compensate differencies in layout.

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

Write\read level adjustment is performed by ddr test

i.MX6/7 DDR Stress Test Tool V3.00 

Best regards
igor
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