DDR Stress Test Failed

[brucesun]

Hi,

We make a board based on i.mx6dlsabreauto but failed for DDR stress test. For DDR component we use MT41K256M16HA-125:E. Can anybody help me with this issue?

Bruce

============================================

        DDR Stress Test (2.0.0)

        Build: Jun 11 2015, 23:33:58

        Freescale Semiconductor, Inc.

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============================================

        Chip ID

DIGPROG(0x020c8260) = 0x00610002

CHIP ID = i.MX6 Solo/DualLite (0x61)

Internal Revision = TO1.2

============================================

============================================

        Boot Configuration

SRC_SBMR1(0x020d8004) = 0x5a003242

SRC_SBMR2(0x020d801c) = 0x31000001

============================================

ARM Clock set to 1GHz

============================================

        DDR configuration

BOOT_CFG3[5-4]: 0x00, Single DDR channel.

DDR type is DDR3

Data width: 64, bank num: 8

Row size: 15, col size: 10

Chip select CSD0 is used

Density per chip select: 2048MB

============================================

Current Tempareture: 52

============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000

Start write leveling calibration...

running Write level HW calibration

Write leveling calibration completed

    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0051004E

    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0045004C

    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x002D002D

    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0028003D

Write DQS delay reult:

   Write DQS0 delay: 78/256 CK

   Write DQS1 delay: 81/256 CK

   Write DQS2 delay: 76/256 CK

   Write DQS3 delay: 69/256 CK

   Write DQS4 delay: 45/256 CK

   Write DQS5 delay: 45/256 CK

   Write DQS6 delay: 61/256 CK

   Write DQS7 delay: 40/256 CK

Starting DQS gating calibration

. . . . . . . . . . . . . . ERROR FOUND, we can't get suitable value !!!!

dram test fails for all values.

Error: failed during ddr calibration

Original Attachment has been moved to: ddr_calibration_20150807-11'54'44.log.zip

Original Attachment has been moved to: MX6DL_ARD_DDR3_register_programming_aid_v0.2.inc.zip

[igorpadykov]

Hi Bruce

if other tests are passed ok, one can skip DQS gating calibration.

In general one can follow next recommendations:

1.  verify the PCB design using "MX6 DRAM Bus Length Check" sheet in

"HW Design Checking List for i.Mx6DQSDL Rev2.7.xlsx"

< https://community.freescale.com/docs/DOC-93819 >

   < https://community.freescale.com/servlet/JiveServlet/downloadBody/93819-102-13-18441/HW%20Design%20Ch... >

2. try using different drive strength for DRAM signals for both  i.MX6 and DRAM part.

3. try different DDR_SEL options  (11 or 10).

Best regards

igor

[BiyongSUN]

What's you ddr layout type fly-by or T-top?

For the fly-by, CK should be longer than the DQS.

And for both type, have you done the bus length check?

please fill the HW Design Checking List for i.MX6DQSDL  MX6 DRAM Bus Length Check for T-top.

And for fly-by, please check manually.  and refer to IMX6DQ6SDLHDG.pdf

use the lastest DDR stress tool and aid.

i.MX6 DDR Stress Test Tool V1.0.3

i.Mx6SL LPDDR2 Script Aid

Freescale i.MX6 DRAM Port Application Guide-DDR3

From the log you show here, I am afraid you have to do the PCB layout again.