Changing eLCDIF clock source on i.MX6ULL

[ivandrobyshevsk]

There's a i.MX6ULL board with connected display with recommended clock of 7MHz. It's set to 7MHz in the device tree (lcdif->display0->display-timings->timing0->clock-frequency), but in reality it's about 8.44 MHz:

pll3_pfd1_540m 1 1 540000000 0 0
   lcdif_pre_sel 1 1 540000000 0 0
     lcdif_pred 1 1 67500000 0 0
      lcdif_podf 1 1 8437500 0 0
        lcdif_pix 1 1 8437500 0 0
        iomuxc 0 0 8437500 0 0
        lcdif_sel 0 0 8437500 0 0

(also confirmed by HW measurements).

This is probably b/c maximum possible divider is 64 (2 3-bit dividers), so with a parent clock of 540MHz minimum we can get is 8.44MHz.

Now, display works fine, but HW team is requesting to lower frequency to recommended 7MHz. Since it's apparently impossible with PLL3 PFD1 parent clock, I'm trying to switch it to PLL3 PFD3, which should be 454 MHz.

First, I've tried to do this via device tree, by adding the following to "lcdif" node:

assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;

assigned-clocks-parents = <&clks IMX6UL_CLK_PLL3_PFD3>;
assigned-clocks-rates = <0>;

It didn't work though, and parent clock was still PFD1, as shown by clk_summary debugfs file.

So I've changed arch/arm/mach-imx/clk-imx6ul.c as follows:

- static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };

+ static const char *lcdif_pre_sels[] = { "pll3_pfd3_454m" };

This works in a sense that clk_summary shows correct parent and frequency:

pll3_pfd3_454m 1 1 454736842 0 0
   lcdif_pre_sel 1 1 454736842 0 0
     lcdif_pred 1 1 56842106 0 0
      lcdif_podf 1 1 7105264 0 0
        lcdif_pix 1 1 7105264 0 0
        iomuxc 0 0 7105264 0 0
        lcdif_sel 0 0 7105264 0 0

But, picture is bad, just a garbage basically. I've tried playing with clock-frequency in the DT but it doesn't help (could it be that PLL3 PFD3 itself needs additional configuration/enabling?).

So basically main question is: how to reduce LCD clock to 7MHz?

Also out of curiosity:  why is PLL3 PFD1 is default parent clock for LCD in the first place? i.MX6ULL reference manual shows on page 618 that it should be PLL2 (see attached pic), and I can't find anything in code to switch it to PLL3.

Note: Linux version is imx_4.1.15_2.0.0_ga

Thanks,

Ivan

[igorpadykov · Accepted solution]

Hi Ivan

one can check below patch which may be helpful:

kernel/git/clk/linux.git - CLK group's fork of linux.git 

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[ivandrobyshevsk]

Hi Igor

Thank you, seems to work: clk_summary in Linux shows correct clock rate, and picture is good. To be confirmed by HW team, but looks good.