Hello,
I am currently studying the i.MX 8M Mini Reference Manual (IMX8MMRM.pdf, Rev. 3, 11/2020) and the NXP BSP, and I have some questions as a BSP beginner.
Q1.
There are some device nodes described in the Reference Manual but not present in the following Device Tree file:
https://github.com/nxp-imx/linux-imx/blob/lf-6.12.y/arch/arm64/boot/dts/freescale/imx8mm.dtsi
Is this because the imx8mm.dtsi file is written specifically for the EVK?
However, there is also an imx8mm-evk.dtsi file in the same directory.
Why are not all nodes defined as listed in Chapter 2 (Memory Map) of the Reference Manual?
For example, the spdif2 node is mentioned in the RM but is not present in the dtsi.
Q2.
The Reference Manual states that only UART1, UART2, and UART3 support SDMA.
However, I found that the uart4 node in imx8mm.dtsi contains properties like dmas and dma-names.
Does this mean that UART4 can actually use DMA?
Q3.
This question is a bit challenging for me as a beginner, so I hope I can describe it properly.
I have two custom boards based on the i.MX 8M Mini.
One board uses the same DRAM as the i.MX8MM EVK (LPDDR4, 2 GB, MT53D512M32D2DS‑053 WT:D) and works without any issues.
The other board uses a different DRAM (Samsung LPDDR4, 4 GB, likely K4FBE3D4HMMGCJ).
The second board always detects only 2 GB of memory instead of 4 GB.
Makefile
Kconfig
xxxx_defconfig
Updated the memory node ranges in both the bootloader DT and kernel DT.
Despite these changes, the system still detects only 2 GB.
Do I need to generate a new lpddr4_pmu_train_*.bin file using the i.MX 8M Family DDR Tool for this Samsung LPDDR4 4 GB memory?
Should I also regenerate the lpddr4_timing_4g.c specifically for this DRAM?
Are there any reference documents or application notes available for this process?
I apologize for the long post, but I wanted to provide as many details as possible to avoid repeated clarification.
Thank you very much for your time and support.
Solved! Go to Solution.
Hi @cmw ,
Hi @cmw ,