About a period of Sync Time of DTACK access of i.MX6

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About a period of Sync Time of DTACK access of i.MX6

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yuuki
Senior Contributor II

Dear all,

We connect an outside device to IM_CS0 of Ei.MX6.

We want to use DTACK access.

We want to know the timing of the access end.

We refer to the following figure.

In these figures, the timing is listed as "Sync Time".

What defines "Sync Time"?


IMX6DQRM.pdf(Rev2):
- 22.8.11 DTACK Mode - AXI Single Access
    Figure 22-15 / Figure 22-16 / Figure 22-17

- 22.8.12 DTACK Mode - AXI Single Write Access
    Figure 22-18

- 22.8.13 DTACK Mode - AXI Burst Access
    Figure 22-19

May I have advice?

Best Regards,
Yuuki

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igorpadykov
NXP Employee
NXP Employee

Hi Yuuki

"Sync Time" is time (2 ACLK cycles for synchronization of internal

circuits)  needed for EIM to recognize valid DTACK level, in particular

it is mentioned in IMX6DQCEC MAXDTI definition.

Best regards

igor

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984 次查看
igorpadykov
NXP Employee
NXP Employee

Hi Yuuki

"Sync Time" is time (2 ACLK cycles for synchronization of internal

circuits)  needed for EIM to recognize valid DTACK level, in particular

it is mentioned in IMX6DQCEC MAXDTI definition.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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