Hello,Community
There are two questions about Table 6-8 Power mode transitions in i.MX 7 Dual Applications Processor Reference Manual.
(1) Does this mean that timer interrupt is enabled by LP Time Alarm Enable in SNVS_LP Control Register (LPCR)?
Which field should I check to see if an interrupt was asserted?
(2) If DP_EN of SNVS_LP Control Register (LPCR), can PMIC_ON_REQ signal be set to 0 in TOP?
Table 6-8. Is the Configuration with internal PMIC column of Power mode transitions Dumb PMIC?
Best reguards
Goto
Solved! Go to Solution.
Hi GoTo
1. yes. It can be checked using SNVS_LPSR bit LPTA
2. yes it is dumb mode, usage TOP and DP_EN can be found in patch on
Q&A: How is mx6 PMIC_ON_REQ under SW control?
Best regards
igor
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Hi GoTo
1. yes. It can be checked using SNVS_LPSR bit LPTA
2. yes it is dumb mode, usage TOP and DP_EN can be found in patch on
Q&A: How is mx6 PMIC_ON_REQ under SW control?
Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
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