Hello,Community
I have two questions.
1.Figure 27 in i.MX 7 Dual Family of Applications Processors Datasheet, Rev. 6
LP5 and LP6 are missing in Table 50. LPDDR3 timing parameters.
Please tell me the parameter value.
2.There is a description of the DRAM_CAS_B signal, but there is no such signal in the LPDDR3 signal.
Is it an address signal?
best regards
Goto
Solved! Go to Solution.
It would be better if you refer JEDEC standard for LPDDR3 timings parameters.
Also, we believe there is a typo in case of DRAM_CAS_B, there is no CAS signal in case of LPDDR3. There should be
DRAM_CAx (command and address bus).
Regards,
Karan Gajjar
It would be better if you refer JEDEC standard for LPDDR3 timings parameters.
Also, we believe there is a typo in case of DRAM_CAS_B, there is no CAS signal in case of LPDDR3. There should be
DRAM_CAx (command and address bus).
Regards,
Karan Gajjar