I am using QSPI_A to access memory. Since the QSPI_A_SS0_B and QSPI_A_SS1_B signals are Chip select1 port0/1 deviceA, shouldn't CS1 on Port A be set to enable? The designer says that CS1 on Port A can be accessed with the disable setting. Is there any problem with this setting?
QSPI_A_SS0_B may be used without QSPI_A_SS1_B. Section 10.2.8.2 (Dual Die Flashes) of i.MX 7Dual Reference Manual (Rev. 1, 01/2018) describes configuration, where both signals are applied.
It's not the answer to what I asked. Is the QSPI_A_SS0_B(QSPI_A_SS1_B) signal valid when the CS1 on Port A setting in Table 6-50 (QuadSPI configuration parameters) is disabled?
The QSPI_A_SS0_B signal is valid when the CS1 on Port A setting in QuadSPI configuration parameters is disabled. QSPI_A_SS1_B is not configured for QSPI in such case.
When the setting value of "CS1 on Port A" in Table 6-50 (QuadSPI configuration parameters) is disabled, is it not possible to use Flash A2 with the following configuration?
If the setting value of "CS1 on Port A" in Table 6-50 (QuadSPI configuration parameters) is enable, can Flash A2 with the following configuration be used?
